mt90826ag2 Zarlink Semiconductor, mt90826ag2 Datasheet - Page 10

• Manufacturer Part Number: mt90826ag2
• Description: Quad Digital Switch
• Manufacturer: Zarlink Semiconductor

Pin Description
66,77,90,101,
135,141,146,
112,125,136,
100,106,111,
117,124,130,
Pin # MQFP
12,22,33,54,
53,60,65,71,
76,84,89,95,
11,21,32,45,
147,157
156
34
35
36
37
38
42
43
D5,D6,D7,D8,D9,
D4,D10,E5,E6,
H4,J4,J10,K5,
F9,G5,G9,H5,
H9,H10,J5,J6,
E7,E8,E9,F5,
F10,G4,G10,
Pin # PBGA
J7,J8,J9,K4
E4,E10,F4,
K6,K7
M12
M13
M11
N12
N13
N11
L11
G7,G8,H5,H6,
D5,D6,D7,E9,
D4,D9,E5,E6,
F7,F8,G5,G6,
F4,F9,G4,H4,
E7,E8,F5,F6,
Pin # LBGA
H7,H8,J4
J6,J7,J8
M10
M11
M12
K10
L10
K11
L11
Zarlink Semiconductor Inc.
MT90826
10
RESET
Name
TRST
TMS
TDO
TCK
V
TDI
IC1
V
DD
ss
+3.3 Volt Power Supply.
Ground.
Test Mode Select (3.3 V Input with
Internal pull-up). JTAG signal that
controls the state transitions of the TAP
controller. This pin is pulled high by an
internal pull-up when not driven.
Test Serial Data In (3.3 V Input with
Internal pull-up). JTAG serial test
instructions and data are shifted in on
this pin. This pin is pulled high by an
internal pull-up when not driven.
Test Serial Data Out (3.3 V Output).
JTAG serial data is output on this pin
on the falling edge of TCK. This pin is
held in high impedance state when
JTAG scan is not enabled.
Test Clock (5 V Tolerant Input).
Provides the clock to the JTAG test
logic.
Test Reset (3.3 V Input with internal
pull-up). Asynchronously initializes the
JTAG TAP controller by putting it in the
Test-Logic-Reset state. This pin is
pulled by an internal pull-up when not
driven. This pin should be pulsed low
on power-up, or held low, to ensure that
the device is in the normal functional
mode.
Internal Connection 1 (3.3 V Input
with internal pull-down). Connect to
V
Device Reset (5 V Tolerant Input).
This input (active LOW) puts the device
in its reset state which clears the
device internal counters and registers.
SS
for normal operation.
Description
Data Sheet