mt9072av2 Zarlink Semiconductor, mt9072av2 Datasheet - Page 78

• Manufacturer Part Number: mt9072av2
• Description: Octal T1/e1/j1 Framer
• Manufacturer: Zarlink Semiconductor

10.1.1.1
The MT9072 includes a CS pin for applications where a single processor is controlling numerous peripherals.
Processor access can be disabled without affecting framer operation. Refer to the CS pin description for details.
An IRQ pin is provided with an extensive suite of maskable interrupts. Refer to the IRQ pin description and the
interrupt section for interrupt processing details.
10.1.2
The ST-BUS is used for data and signaling access only and does not carry any MT9072 control information.
Payload data is accessed through the DSTi and DSTo streams. Channel Associate Signalling bits and Common
Channel Signaling bits can be accessed through CSTi and CSTo streams. See Tables 2 to 6 for ST-BUS Channel to
transmit/receive timeslot mapping.
Dedicated data link pins are included which provide the user the option of bypassing the receive elastic buffer and
accessing data link (DL) data with an external controller. The MT9072 provides numerous additional methods for
accessing the DL, refer to the data link sections for details.
10.1.3
In the IMA (Inverse Mux for ATM) mode the transmit and receive timing on the backplane are independent unlike
the ST-BUS where all of the streams (DSTi/DSTo) are synchronous with a single clock (CKI) and a single frame
pulse (FPI). The IMA mode is specifically intended to interface to the Zarlink IMA devices such as MT90220.
In IMA mode the RXBF and RXDLC pins provide the receive frame pulse and receive clock for the data appearing
at the DSTo pin. The FPi and CKi pins are inputs for the transmit frame pulse and transmit clock for data appearing
at the DSTi pin.
Note that in the IMA Mode, the slip buffers will be bypassed. On the transmit side data is accepted in the DSTi
streams with respect to the CKi clock. The transmit clock TXCL (an input clock in T1 Mode) has to be synchronous
to the CKi clock. On the receive side the EXCLi clock is the master and the DSTo data is synchronous to the EXCLi
clock.
In T1 IMA mode the backplane operates at 1.544 Mbit/s with the frame pulse centered on the S-Bit, the timing
diagrams are shown in Figures 32 and 33. In order to provide the extracted 1.544 Mbit/s clock the E1.5CK bit in the
Data Link Control Register (Y06) must be set. The receive and transmit slip buffers are bypassed in this mode.
In E1 IMA mode the backplane operates at 2.048 Mbit/s in a manner similar to the ST-BUS, the timing diagrams are
shown in Figures 51 and 52. The receive slip buffer is bypassed in this mode.
Note that in IMA mode the ST-BUS selection in register 900 is ignored.
If IMA mode is selected the following functions are not supported:
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8.192 Mbits backplane mode
Robbed bit signaling and CAS
Digital milliwat patterns
One, two second timers and latching of counters at 1 sec timer
GCI mode
Data link insertion extraction of FDL (the HDLC can be assigned to the FDL IMA mode)
ST-BUS Interface (DSTi, DSTo, CSTi, CSTo Pins)
IMA Interface (DSTi, DSTo, Pins)
CS and IRQ
Zarlink Semiconductor Inc.
MT9072
78
Data Sheet