am79c984a Advanced Micro Devices, am79c984a Datasheet - Page 17

• Manufacturer Part Number: am79c984a
• Description: Enhanced Integrated Multiport Repeater Eimr
• Manufacturer: Advanced Micro Devices

external filter modules. Proper termination is shown in
the Systems Applications section.
The receiver’s threshold voltage can be programmed to
an extended-distance mode. In this mode, the differen-
tial receiver’s threshold is reduced to allow a longer
cable than the 100 meters specified in the IEEE 802.3
standard. For programming details, refer to the Control
Commands section.
Link Test
The integrated TP ports implement the Link Test func-
tion, as specified in the IEEE 802.3 10BASE-T stan-
dard. The eIMR device will transmit Link Test pulses to
any TP port after that port’s transmitter has been inac-
tive for more than 8 ms to 17 ms. Conversely, if a TP
port does not receive any data packets or Link Test
pulses for more than 65 ms to 132 ms and the Link Test
function is enabled for that port, then that port will enter
the link-fail state. The eIMR device will disable a port in
link-fail state (i.e., disable repeater transmit and receive
functions) until it receives either four consecutive Link
Test pulses or a data packet.
The Link Test function can be disabled via the eIMR
control port on a port-by-port basis, to allow the eIMR
device to operate with pre-10BASE-T networks that do
not implement the Link Test function. When the Link
Test function is disabled, the eIMR device will not allow
the TP port to enter link-fail state, even if no Link Test
pulses or data packets are being received. Note, how-
ever, that the eIMR device will always transmit Link Test
pulses to all TP ports, regardless of whether or not the
port is enabled, partitioned, in link-fail state, or has its
Link Test function disabled. Separate control com-
mands exist for enabling and disabling the transmission
of Link Test pulses on a port-by-port basis.
Polarity Reversal
The TP ports can be programmed to receive data if a
wiring error results in a data packet being received at a
TP port with reversed polarity. This function will be en-
abled upon reception of a negative End Transmit Delim-
iter (ETD) or negative pulses and allows subsequent
packets to be received with the correct polarity. The po-
larity-reversal function is executed once following reset
or link-fail and can be programmed via the control port
to be enabled or disabled on a port-by-port basis. The
function may be enabled or disabled, following a reset,
depending on the level of the SI signal on the rising
edge of the RST pulse.
P R E L I M I N A R Y
Am79C984A
Visual Status Monitoring (LED) Support
The eIMR status port can be connected to LEDs to fa-
cilitate the visual monitoring of repeater port status.
The status port has twelve output signals, LDA
LDB
sent the four TP ports and AUI port. LDGA and LDGB
are global indicators. Attributes that may be monitored
are Carrier Sense (CRS), Collision (COL), Partition
(PAR), Link Status (LINK), Loopback (LB), Port Dis-
abled (DIS), and Jabber (JAB). Three control bits,
LDC
on the LEDs. Table 2 shows how the programming
combinations for LDC
be monitored.
Each LED drive pin (LDGA, LDGB, LDA
has two states: Off and LOW. When none of the se-
lected attributes are true, the driver is off and the diode
is unlit. When an attribute is true, the driver is LOW, and
the corresponding LEDs in Bank A or Bank B will be lit.
Some of the settings (LDC
tion. This allows two attributes to be selected for a given
state on the pin. As an example when LDC
the LDA outputs relating to TP ports will be solidly lit
when there is a link established at that port. However,
whenever there is activity on a port, the corresponding
LDA pin will switch on (LOW) and off at a period of 130
ms. Note that a partition on that port will also cause the
pin to go LOW.
On LDC settings that have two attributes for a state on
a pin (blink or solid-on), the attribute causing the output
to blink has priority. (Those attributes are shown in
Table 2 with a blink period specified next to it.) If an at-
tribute has no blink period specified, the LED indicates
the attribute by being solidly lit.
The LEDs can also be controlled via the control port.
The Enable Software Override commands turn the
LEDs on regardless of the attributes selected for dis-
play through the LDC setting. Enable Software Over-
ride of Bank A LEDs causes the LDA
to be driven LOW, and Enable Software Override of
Bank B LEDs causes the LDB
driven LOW. The blink rate is set by the Software Over-
ride LED Blink Rate command. The periods are off,
512 ms, 1560 ms, or solid on.
0-4
0-2
, LDGA, and LDGB. LDA
, select the particular attributes to be displayed
0-2
control the attributes that will
2
= 1) include a blink func-
0-4
0-4
and LDGB pins to be
and LDB
0-4
0-4
and LDGA pins
, and LDB
0-2
0-4
0-4
= 110,
repre-
, and
0-4
17
)