89hpes34h16 Integrated Device Technology, 89hpes34h16 Datasheet - Page 9

• Manufacturer Part Number: 89hpes34h16
• Description: 34-lane, 16-port Pcie System Interconnect Switch
• Manufacturer: Integrated Device Technology

IDT 89HPES34H16 Data Sheet
MSMBSMODE
SWMODE[3:0]
P01MERGEN
P23MERGEN
P45MERGEN
JTAG_TCK
JTAG_TDI
RSTHALT
Signal
CCLKDS
CCLKUS
PERSTN
Signal
Type
Type
I
I
I
I
I
I
I
I
I
I
I
Common Clock Downstream. When the CCLKDS pin is asserted, it indicates that a
common clock is being used between the downstream device and the downstream
port.
Common Clock Upstream. When the CCLKUS pin is asserted, it indicates that a
common clock is being used between the upstream device and the upstream port.
Master SMBus Slow Mode. The assertion of this pin indicates that the master SMBus
should operate at 100 KHz instead of 400 KHz. This value may not be overridden.
Port 0 and 1 Merge. When this pin is asserted, port 1 is merged with port 0 to form a
single x8 port. The SerDes lanes associated with port B become lanes 4 through 7 of
port 0.
Port 2 and 3 Merge. When this pin is asserted, port 3 is merged with port 2 to form a
single x8 port. The SerDes lanes associated with port D become lanes 4 through 7 of
port 2.
Port 4 and 5 Merge. When this pin is asserted, port 5 is merged with port 4 to form a
single x8 port. The SerDes lanes associated with port F become lanes 4 through 7 of
port 4.
Fundamental Reset. Assertion of this signal resets all logic inside the PES34H16 and
initiates a PCI Express fundamental reset.
Reset Halt. When this signal is asserted during a PCI Express fundamental reset, the
PES34H16 executes the reset procedure and remains in a reset state with the Master
and Slave SMBuses active. This allows software to read and write registers internal to
the device before normal device operation begins. The device exits the reset state
when the RSTHALT bit is cleared in the PA_SWCTL register by an SMBus master.
Switch Mode. These configuration pins determine the PES34H16 switch operating
mode.
JTAG Clock. This is an input test clock used to clock the shifting of data into or out of
the boundary scan logic or JTAG Controller. JTAG_TCK is independent of the system
clock with a nominal 50% duty cycle.
JTAG Data Input. This is the serial data input to the boundary scan logic or JTAG
Controller.
0x0 - Normal switch mode
0x1 - Normal switch mode with Serial EEPROM initialization
0x2 through 0x7 - Reserved
0x8 - Normal switch mode with upstream port failover (port 0 selected as the
0x9 - Normal switch mode with upstream port failover (port 2 selected as the
0xA - Normal switch mode with Serial EEPROM initialization and upstream port
0xB - Normal switch mode with Serial EEPROM initialization and upstream port
0xC through 0xF - Reserved
upstream port)
upstream port)
failover (port 0 selected as the upstream port)
failover (port 2 selected as the upstream port)
Table 6 Test Pins (Part 1 of 2)
Table 5 System Pins
9 of 45
Name/Description
Name/Description
April 16, 2008