njg1524pc1 ETC-unknow, njg1524pc1 Datasheet - Page 3

• Manufacturer Part Number: njg1524pc1
• Description: Dpdt Switch Gaas Mmic
• Manufacturer: ETC-unknow

TERMINAL INFORMATION
13, 15, 16
5, 6, 8,
No.
10
11
12
14
1
2
3
4
7
9
SYMBOL
VCTL1
VCTL2
VCTL1
GND
PA2
PB2
PC2
PB1
PA1
PC1
NC
RF port A2. This port is connected with PC1 port by controlling V
to -0.2~+0.2V and V
voltage of internal circuit, an external capacitor is required.
Control port 1. The voltage of this port controls PC1 to PA1/PA2 and
PC2 to PB1/PB2 state. The ‘ ON’ and ‘ OFF’ state is toggled by
controlling voltage of this terminal to high-state (2.5~6.5V) or low-
state (-0.2~+0.2V). The voltage of VCTL2 should be set to opposite
state. The bypass capacitor should be connected with GND as close
as possible for excellent RF performance.
Control port 2. The voltage of this port controls PC1 to PA1/PA2 and
PC2 to PB1/PB2 state. The ‘ ON’ and ‘ OFF’ state is toggled by
controlling voltage of this terminal to high-state (2.5~6.5V) or low-
state (-0.2~+0.2V). The voltage of VCTL1 should be set to opposite
state. The bypass capacitor should be connected with GND as close
as possible for excellent RF performance.
RF port B2. This port is connected with PC2 port by controlling
VCTL1 to -0.2~+0.2V and VCTL2 to 2.5~6.5V. In order to block the
DC bias voltage of internal circuit, an external capacitor is required.
Common RF port C2. In order to block the DC bias voltage of internal
circuit, an external capacitor is required.
RF port B1. This port is connected with PC1 port by controlling
VCTL2 to -0.2~+0.2V and VCTL1 to 2.5~6.5V. In order to block the
DC bias voltage of internal circuit, an external capacitor is required.
No connected terminal.
Control port 1. The voltage of this port controls PC1 to PA1/PA2 and
PC2 to PB1/PB2 state. The ‘ ON’ and ‘ OFF’ state is toggled by
controlling voltage of this terminal to high-state (2.5~6.5V) or low-
state (-0.2~+0.2V). The voltage of V
state. The bypass capacitor should be connected with GND as close
as possible for excellent RF performance.
RF port A1. This port is connected with PC1 port by controlling
VCTL2 to -0.2~+0.2V and VCTL1 to 2.5~6.5V. In order to block the
DC bias voltage of internal circuit, an external capacitor is required.
Common RF port C1. In order to block the DC bias voltage of internal
circuit, an external capacitor is required.
Ground terminal. Please connect this terminal with ground plane as
close as possible for excellent RF performance.
CTL (H)
DESCRIPTIONS
to 2.5~6.5V. In order to block the DC bias
CTL2
should be set to opposite
NJG1524PC1
CTL (L)
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