scn68562 NXP Semiconductors, scn68562 Datasheet - Page 2

• Manufacturer Part Number: scn68562
• Description: Dual Universal Serial Communications Controller Duscc
• Manufacturer: NXP Semiconductors

Philips Semiconductors
DESCRIPTION
The Philips Semiconductors SCN68562 Dual Universal Serial
Communications Controller (DUSCC) is a single-chip MOS-LSI
communications device that provides two independent,
multi-protocol, full-duplex receiver/transmitter channels in a single
package. It supports bit-oriented and character-oriented (byte count
and byte control) synchronous data link controls as well as
asynchronous protocols. The SCN68562 interfaces to the 68000
MPUs via asynchronous bus control signals and is capable of
program-polled, interrupt driven, block-move or DMA data transfers.
The operating mode and data format of each channel can be
programmed independently.
Each channel consists of a receiver, a transmitter, a 16-bit
multifunction counter/timer, a digital phase-locked loop (DPLL), a
parity/CRC generator and checker, and associated control circuits.
The two channels share a common bit rate generator (BRG),
operating directly from a crystal or an external clock, which provides
16 common bit rates simultaneously. The operating rate for the
receiver and transmitter of each channel can be independently
selected from the BRG, the DPLL, the counter/timer, or from an
external 1X or 16X clock, making the DUSCC well suited for
dual-speed channel applications. Data rates up to 4Mbits per
second are supported.
PIN CONFIGURATIONS
1995 May 01
Dual universal serial communications controller (DUSCC)
GPO2BN/RTSBN
CTSBN/LCBN
RTxDRQBN/
RTxDAKBN/
SYNOUTBN
TxDRQBN/
TxDAKBN/
GPO1BN
DTACKN
RESETN
DCDBN/
GPI1BN
RTSBN/
SYNIBN
GPI2BN
TRxCB
RTxCB
IACKN
RxDB
DTCN
TxDB
IRQN
GND
A3
A2
A1
D7
D6
D5
D4
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
N PACKAGE
DIP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
V
A4
A5
A6
RTxDAKAN/
GPI1AN
X1/CLK
X2/IDCN
RTSAN/
SYNOUTAN
TRxCA
RTxCA
DCDAN/
SYNIAN
Rxda
TxDA
TxDAKAN/
GPI2AN
RTxDRQAN/
GPO1AN
TxDRQAN/
GPO2AN/RTSAN
CTSAN/LCAN
D0
D1
D2
D3
DONEN
R/WN
CSN
DD
Figure 1. Pin Configurations
2
The transmitter and receiver each contain a four-deep FIFO with
appended transmitter command and receiver status bits and a shift
register. This permits reading and writing of up to four characters at
a time, minimizing the potential of receiver overrun or transmitter
underrun, and reducing interrupt or DMA overhead. In addition, a
flow control capability is provided to disable a remote transmitter
when the FIFO of the local receiving device is full.
Two modem control inputs (DCD and CTS) and three modem
control outputs are provided. These inputs and outputs can be
optionally programmed for other functions.
FEATURES
General Features
Dual full-duplex synchronous/asynchronous receiver and
transmitter
Multiprotocol operation
– BOP: HDLC/ADCCP, SDLC, SDLC loop, X.25 or X.75 link level,
– COP: BISYNC, DDCMP
– ASYNC: 5–8 bits plus optional parity
Four character receiver and transmitter FIFOs
etc.
CORNER
INDEX
Pin Function
10 TRxCB
11 RTxCB
12 DCDBN/
13 NC
14 RxDB
15 TxDB
16 TxDAKBN/
17 RTxDRQBN/
18 TxDRQBN/
19 CTSBN/LCBN
20 D7
21 D6
22 D5
23 D4
24 DTACKN
25 DTCN
26 GND
1
2
3
4
5
6
7
8
9
IACKN
A3
A2
A1
RTxDAKBN/
GPI1BN
IRQN
NC
RESETN
RTSBN/
SYNOUTBN
SYNIBN
GPI2BN
GPO1BN
GPO2BN/RTSBN
20
8
21
7
A PACKAGE
TOP VIEW
PLCC
1
Pin Function
27 CSN
28 R/WN
29 DONEN
30 D3
31 D2
32 D1
33 D0
34 NC
35 CTSAN/LCAN
36 TxDRQAN/
37 RTxDRQAN/
38 TxDAKAN/
39 TxDA
40 RxDA
41 NC
42 DCDAN/
43 RTxCA
44 TRxCA
45 RTSAN/
46 X2/IDCN
47 X1/CLK
48 RTxDAKAN/
49 A6
50 A5
51 A4
52 V
GPO2AN/RTSAN
GPO1AN
GPI2AN
SYNIAN
SYNOUTAN
GPI1AN
DD
47
33
46
34
Product specification
SCN68562
853-0831 15179
SD00222