k4t1g084qa-zce6 Samsung Semiconductor, Inc., k4t1g084qa-zce6 Datasheet - Page 16

• Manufacturer Part Number: k4t1g084qa-zce6
• Description: 1gb A-die Ddr2 Sdram Specification
• Manufacturer: Samsung Semiconductor, Inc.

1G A-die DDR2 SDRAM
Notes :
1. IDD specifications are tested after the device is properly initialized
2. Input slew rate is specified by AC Parametric Test Condition
3. IDD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS, DQS\, RDQS, RDQS\, LDQS, LDQS\, UDQS, and UDQS\. IDD values must be met with all combinations of EMRS
5. Definitions for IDD
For purposes of IDD testing, the following parameters are utilized
Detailed IDD7
The detailed timings are shown below for IDD7.
Legend: A = Active; RA = Read with Autoprecharge; D = Deselect
IDD7: Operating Current: All Bank Interleave Read operation
All banks are being interleaved at minimum t RC(IDD) without violating t RRD(IDD) and t FAW(IDD) using a burst length of 4. Control and address bus
inputs are STABLE during DESELECTs. IOUT = 0mA
Timing Patterns for 8bank devices x4/ x8
-DDR2-400 3/3/3 : A0 RA0 A1 RA1 A2 RA2 A3 RA3 A4 RA4 A5 RA5 A6 RA6 A7 RA7
-DDR2-533 4/4/4 : A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D A4 RA4 A5 RA5 A6 RA6 A7 RA7 D D
-DDR2-667 5/5/5 : A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D
Timing Patterns for 8bank devices x16
-DDR2-400 3/3/3 : A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D A4 RA4 A5 RA5 A6 RA6 A7 RA7 D D
-DDR2-533 4/4/4 : A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D D
-DDR2-667 5/5/5 : A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D D
bits 10 and 11.
LOW is defined as Vind VILAC(max)
HIGH is defined as Vin tVIHAC(min)
STABLE is defined as inputs stable at a HIGH or LOW level
FLOATING is defined as inputs at VREF = VDDQ/2
SWITCHING is defined as:
t RRD(IDD)-x4/x8
t RRD(IDD)-x16
t RASmin(IDD)
Parameter
t RCD(IDD)
t RFC(IDD)
t RC(IDD)
t CK(IDD)
t RP(IDD)
CL(IDD)
inputs changing between HIGH and LOW every other data transfer (once per clock) for DQ signals not including masks or strobes.
inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and control signals, and
DDR2-667
127.5
5-5-5
7.5
15
60
10
45
15
5
3
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DDR2-533
127.5
4-4-4
3.75
7.5
15
60
10
45
15
4
DDR2-400
127.5
3-3-3
7.5
15
55
10
40
15
3
5
Units
tCK
ns
ns
ns
ns
ns
ns
ns
ns
DDR2 SDRAM
Rev. 1.1 Aug. 2005