k4t1g084qa-zce60 Samsung Semiconductor, Inc., k4t1g084qa-zce60 Datasheet - Page 22

• Manufacturer Part Number: k4t1g084qa-zce60
• Description: 1gb A-die Ddr2 Sdram
• Manufacturer: Samsung Semiconductor, Inc.

1G A-die DDR2 SDRAM
4. Differential data strobe
bit; timing advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM
dependent. In single ended mode, timing relationships are measured relative to the rising or falling
these timing relationships are measured relative to the crosspoint of DQS and its
design and characterization. Note that when differential data
nally to VSS through a 20 ohm to 10 K ohm resisor to insure proper operation.
5. AC timings are for linear signal transitions.
6. These parameters guarantee device behavior, but they are not necessarily tested on each device. They may be guaranteed by device design or tester
correlation.
7. All voltages are referenced to VSS.
8. Tests for AC timing, IDD, and electrical (AC and DC) characteristics, may be conducted at nominal reference/supply voltage levels, but the related
specifications and device operation are guaranteed for the full voltage range specified.
DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMRS
CK/CK
DQS/DQS
DQ
DQS/
DQS
DQ
DM
CK
CK
DQS
DQS
t
CH
t
RPRE
t
DQS
DQS
WPRE
V
V
t
t
CL
IH
DQSQmax
IL
(ac)
(ac)
<Data output (read) timing>
t
strobe mode is disabled via the EMRS, the complementary pin, DQS, must be tied exter-
DMin
DS
D
<Data input (write) timing>
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t
DQSH
V
t
V
QH
IH
IL
(ac)
Q
(ac)
DMin
t
DS
D
t
complement, DQS. This distinction in timing methods is guaranteed by
DQSL
Q
DMin
D
t
DH
V
V
IH
IL
(dc)
(dc)
t
DQSQmax
Q
edges of DQS crossing at VREF. In differential mode,
DMin
D
t
DH
V
V
IH
IL
t
(dc)
WPST
(dc)
t
t
RPST
QH
Q
pin timings are measured is mode
DDR2 SDRAM
Rev. 1.1 Aug. 2005
“Enable DQS” mode