k4t51043qg-hcf7 Samsung Semiconductor, Inc., k4t51043qg-hcf7 Datasheet - Page 33

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k4t51043qg-hcf7

Manufacturer Part Number
k4t51043qg-hcf7
Description
512mb G-die Ddr2 Sdram Specification
Manufacturer
Samsung Semiconductor, Inc.
Datasheet
K4T51043QG
K4T51083QG
K4T51163QG
DQS
Note1
Hold Slew Rate
Note : DQS signal must be monotonic between Vil(dc)max and Vih(dc)min.
Rising Signal
V
V
V
V
V
V
IL(dc)
IL(ac)
DDQ
REF(dc)
IH(ac)
IH(dc)
Figure 12 - IIIustration of tangent line for tDH (single-ended DQS)
max
max
V
V
V
V
V
V
V
min
min
DDQ
IH(ac)
IH(dc)
REF(dc)
IL(dc)
IL(ac)
SS
V
SS
max
max
=
min
min
dc to V
dc to V
region
region
tangent line [ V
REF
REF
∆TR
tDS
REF(dc)
tangent
line
- Vil(dc)max ]
tDH
33 of 45
Hold Slew Rate
Falling Signal
∆TR
nominal
line
=
tangent line [ Vih(dc)min - V
tDS
tangent
line
tDH
∆TF
∆TF
nominal
line
Rev. 1.21 February 2008
DDR2 SDRAM
REF(dc)
]

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