k4t56083qf Samsung Semiconductor, Inc., k4t56083qf Datasheet - Page 20

• Manufacturer Part Number: k4t56083qf
• Description: 256mb F-die Ddr2 Sdram
• Manufacturer: Samsung Semiconductor, Inc.

256Mb F-die DDR2 SDRAM
General notes, which may apply for all AC parameters
1. Slew Rate Measurement Levels
2. DDR2 SDRAM AC timing reference load
part. It is not intended to be either a precise representation of the typical system environment or a depiction of
the actual load presented by a production tester. System designers will use IBIS or other simulation tools to
correlate the timing reference load to a system environment. Manufacturers will correlate to their production
test conditions (generally a coaxial transmission line terminated at the tester electronics).
The output timing reference voltage level for single ended signals is the crosspoint with VTT. The output tim-
ing reference voltage level for differential signals is the crosspoint of the true (e.g. DQS) and the complement
(e.g. DQS) signal.
3. DDR2 SDRAM output slew rate test load
Following figure represents the timing reference load used in defining the relevant timing parameters of the
a. Output slew rate for falling and rising edges is measured between VTT - 250 mV and VTT + 250 mV for
b. Input slew rate for single ended signals is measured from dc-level to ac-level: from V
c. VID is the magnitude of the difference between the input voltage on CK and the input voltage on CK, or
Output slew rate is characterized under the test conditions as shown in the following figure.
single ended signals. For differential signals (e.g. DQS - DQS) output slew rate is measured between
DQS - DQS = -500 mV and DQS - DQS = +500mV. Output slew rate is guaranteed by design, but is not
necessarily tested on each device.
V
between DQS and DQS for differential strobe.
For differential signals (e.g. CK - CK) slew rate for rising edges is measured from CK - CK = -250 mV to
CK - CK = +500 mV (250mV to -500 mV for falling edges).
IH
(ac) for rising edges and from V
VDDQ
VDDQ
DUT
DUT
RDQS, RDQS
DQS, DQS
RDQS
RDQS
DQS
DQS
DQ
DQ
IH
<AC Timing Reference Load>
Output
Output
(dc) and V
<Slew Rate Test Load>
Test point
Timing
reference
point
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IL
(ac) for falling edges.
25
25
:
:
V
V
TT
TT
= V
= V
DDQ
DDQ
/2
/2
Rev. 1.5 Feb. 2005
DDR2 SDRAM
IL
(dc) to