k4t56163qi Samsung Semiconductor, Inc., k4t56163qi Datasheet - Page 32

• Manufacturer Part Number: k4t56163qi
• Description: 256mb I-die Ddr2 Sdram
• Manufacturer: Samsung Semiconductor, Inc.

Table 5 - Derating values for DDR2-667, DDR2-800
For all input signals the total tIS (setup time) and tIH (hold time) required is calculated by adding the data sheet tIS(base) and tIH(base) value to the ∆tIS
and ∆tIH derating value respectively. Example: tIS (total setup time) = tIS(base) + ∆tIS
Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(dc) and the first crossing of Vih(ac)min.
Setup (tIS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(dc) and the first crossing of Vil(ac)max. If
the actual signal is always earlier than the nominal slew rate line between shaded ’VREF(dc) to ac region’, use nominal slew rate for derating value (see
Figure 13). If the actual signal is later than the nominal slew rate line anywhere between shaded ’VREF(dc) to ac region’, the slew rate of a tangent line to
the actual signal from the ac level to dc level is used for derating value (see Figure 14).
Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of Vil(dc)max and the first crossing of VREF(dc). Hold
(tIH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of Vih(dc)min and the first crossing of VREF(dc). If the
actual signal is always later than the nominal slewrate line between shaded ’dc to VREF(dc) region’, use nominal slew rate for derating value (see Figure
15). If the actual signal is earlier than the nominal slew rate line anywhere between shaded ’dc to VREF(dc) region’, the slew rate of a tangent line to the
actual signal from the dc level to VREF(dc) level is used for derating value (see Figure 16).
Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/IL(ac) at the time of the rising clock
transition) a valid input signal is still required to complete the transition and reach VIH/IL(ac).
For slew rates in between the values listed in Tables 4 and 5, the derating values may obtained by linear interpolation.
These values are typically not subject to production test. They are verified by design and characterization.
K4T56163QI
Address Slew
Command/
rate(V/ns)
0.25
0.15
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
-1000
+150
+143
+133
+120
+100
-100
-168
-200
-325
-517
∆tIS
+67
-13
-22
-34
-60
-5
0
2.0 V/ns
∆tIS and ∆tIH Derating Values for DDR2-667, DDR2-800
-1125
-125
-188
-292
-375
-500
-708
∆tIH
+94
+89
+83
+75
+45
+21
-14
-31
-54
-83
0
+180
+173
+163
+150
+130
∆tIS
-138
-170
-295
-487
-970
+97
+30
+25
+17
-30
-70
+8
-4
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1.5 V/ns
CK, CK Differential Slew Rate
-1095
+124
+119
+113
+105
∆tIH
-158
-262
-345
-470
-678
+75
+51
+30
+16
-24
-53
-95
-1
+210
+203
+193
+180
+160
+127
-108
-140
-265
-457
-940
∆tIS
+60
+55
+47
+38
+26
-40
0
1.0 V/ns
-1065
+154
+149
+143
+135
+105
-128
-232
-315
-440
-648
∆tIH
+81
+60
+46
+29
-23
-65
+6
Rev. 1.0 October 2007
DDR2 SDRAM
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