k4d261638k Samsung Semiconductor, Inc., k4d261638k Datasheet - Page 5

• Manufacturer Part Number: k4d261638k
• Description: 128mbit Gddr Sdram
• Manufacturer: Samsung Semiconductor, Inc.

K4D261638K
5.0 INPUT/OUTPUT FUNCTIONAL DESCRIPTION
*1 : The timing reference point for the differential clocking is the cross point of CK and CK.
LDQS,UDQS
DQ
V
LDM,UDM
CK, CK
BA
A
V
DDQ
NC/RFU
Symbol
For any applications using the single ended clocking, apply V
0
0
DD
V
CKE
RAS
CAS
WE
0
CS
~ DQ
~ A
REF
, BA
/V
/V
SS
SSQ
11
*1
1
15
Reserved for future use
No connection/
Power Supply
Power Supply
Power Supply
Input/Output
Input/Output
Type
Input
Input
Input
Input
Input
Input
Input
Input
Input
The differential system clock Input.
All of the inputs are sampled on the rising edge of the clock except DQ’s and DM’s that are
sampled on both edges of the DQS.
Activates the CK signal when high and deactivates the CK signal when low. By deactivating
the clock, CKE low indicates the Power down mode or Self refresh mode.
CS enables the command decoder when low and disabled the command decoder when high.
When the command decoder is disabled, new commands are ignored but previous operations
continue.
Latches row addresses on the positive going edge of the CK with RAS low. Enables row
access & precharge.
Latches column addresses on the positive going edge of the CK with CAS low. Enables col-
umn access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Data input and output are synchronized with both edge of DQS.
For the x16, LDQS corresponds to the data on DQ0-DQ7 ; UDQS corresponds to the data on
DQ8-DQ15.
Data in Mask. Data In is masked by DM Latency=0 when DM is
high in burst write. For the x16, LDM corresponds to the data on DQ0-DQ7 ; UDM correspons
to the data on DQ8-DQ15.
Data inputs/Outputs are multiplexed on the same pins.
Selects which bank is to be active.
Row/Column addresses are multiplexed on the same pins.
Row addresses : RA
Power and ground for the input buffers and core logic.
Isolated power supply and ground for the output buffers to provide improved noise immunity.
Reference voltage for inputs, used for SSTL interface.
This pin is recommended to be left "No connection" on the device
REF
0
to CK pin.
~ RA
- 5 /19 -
11
, Column addresses : CA
Function
0
128M GDDR SDRAM
~ CA
8
.
Rev. 1.3 July 2007