ic42s32400 ETC-unknow, ic42s32400 Datasheet - Page 28

• Manufacturer Part Number: ic42s32400
• Description: 1m X 32 Bit X 4 Banks 128-mbit Sdram
• Manufacturer: ETC-unknow

IC42S32400
IC42S32400L
Figure 5.Self Refresh Entry &Exit Cycle
28
BS0,1
A0-A9
DQM
RAS#
CAS#
WE#
CLK
CKE
CS#
Note:To Enter SelfRefresh Mode
1. CS#,RAS#&CAS#with CKE should be low at the same clock cycle.
2. After 1 clock cycle,all the inputs including the system clock can be don ’t care except for CKE.
3. The device remains in SelfRefresh mode as long as CKE stays “low”.
To Exit SelfRefresh Mode
4. System clock restart and be stable before returning CKE high.
5. Enable CKE and CKE should be set high for minimum time of tSRX.
6. CS#starts from high.
7. Minimum tRC is required after CKE going high to complete SelfRefresh exit.
8. 4096 cycles of burst AutoRefresh is required before SelfRefresh entry and after SelfRefresh exit if the system uses burst refresh.
DQ
Once the device enters SelfRefresh mode,minimum tRAS is required before exit from SelfRefresh.
T0
*Note 8
SelfRefresh Enter
*Note 1
T1
t
IS
Hi-Z
T2
*Note 2
T3
T4
T5
T6
*Note 3
T7
T8
T9
T10
Hi-Z
*Note 4
SelfRefresh Exit
T11
*Note 5
t
*Note 6
SRX
T12
t
RC(min) *Note 7
T13
T14
Auto Refresh
T15
*Note 8
t
T16
PDE
Integrated Circuit Solution Inc.
T17
T18
T19
DR038-0C 02/01/2005