mt18vddt12872dg-265 Micron Semiconductor Products, mt18vddt12872dg-265 Datasheet - Page 13

• Manufacturer Part Number: mt18vddt12872dg-265
• Description: 256mb, 512mb, 1gb, 2gb X72, Ecc, Dr 184-pin Ddr Rdimm
• Manufacturer: Micron Semiconductor Products

Table 14:
PDF: 09005aef80e1141d/Source: 09005aef80e11353
DD18C32_64_128_256x72D.fm - Rev. D 4/08 EN
Parameter/Condition
Operating one bank active-precharge current:
t
Address and control inputs changing once every two clock cycles
Operating one bank active-read-precharge current: BL = 2;
t
changing once per clock cycle
Precharge power-down standby current: All device banks idle; Power-
down mode;
Idle standby current: CS# = HIGH; All device banks idle;
CKE = HIGH; Address and other control inputs changing once per clock cycle;
V
Active power-down standby current: One device bank active; Power-
down mode;
Active standby current: CS# = HIGH; CKE = HIGH; One device bank active;
t
per clock cycle; Address and other control inputs changing once per clock
cycle
Operating burst read current: BL = 2; Continuous burst reads; One device
bank active; Address and control inputs changing once per clock cycle;
t
Operating burst write current: BL = 2; Continuous burst writes; One
device bank active; Address and control inputs changing once per clock
cycle;
cycle
Auto refresh current
Self refresh current: CKE ≤ 0.2V
Operating bank interleave read current: Four device bank interleaving
reads (BL = 4) with auto precharge;
Address and control inputs change only during active READ or WRITE
commands
CK =
RC =
RC =
CK =
IN
= V
t
t
t
t
t
RAS (MAX);
RC (MIN);
CK (MIN); DQ, DM, and DQS inputs changing once per clock cycle;
CK (MIN); I
CK =
REF
for DQ, DM, and DQS
t
CK (MIN); DQ, DM, and DQS inputs changing twice per clock
t
t
I
Values are for the MT46V128M8 DDR SDRAM only and are computed from values specified in the
1Gb (128 Meg x 8) component data sheet
CK =
CK =
DD
t
CK =
OUT
Specifications and Conditions – 2GB
t
Notes:
CK =
t
t
CK (MIN); CKE = LOW
CK (MIN); CKE = LOW
= 0mA
t
CK (MIN); I
t
CK (MIN); DQ, DM, and DQS inputs changing twice
1. Value calculated as one module rank in this operating condition; all other module ranks in
2. Value calculated reflects all module ranks in this operating condition.
I
DD
OUT
2P (CKE LOW) mode.
t
RC =
256MB, 512MB, 1GB, 2GB (x72, ECC, DR) 184-Pin DDR RDIMM
= 0mA; Address and control inputs
t
RC (MIN);
t
RC =
t
CK =
t
t
REFC =
REFC = 7.8125µs
t
RC (MIN);
t
t
CK =
CK (MIN);
13
t
RFC (MIN)
t
CK (MIN);
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Symbol -335
I
I
I
I
I
I
I
DD
DD
DD
DD
I
I
DD
DD
DD
I
I
I
DD
DD
DD
DD
DD
4W
3N
5A
2P
3P
4R
2F
0
1
5
6
7
1
1
2
2
1
2
2
2
1
2
2
1
1,530 1,215 1,395 1,305
1,845 1,485 1,710 1,620
1,170
2,070 1,530 1,890 1,620
2,160 1,440 1,980 1,710
6,120 5,220 5,940 5,130
4,815 3,645 4,455 4,230
180
630
900
180
162
Electrical Specifications
-262
©2003 Micron Technology, Inc. All rights reserved
810
630
810
180
90
90
-26A/
1,080
-265
180
540
810
180
162
-202
180
990
450
720
180
162
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA