mt18vddt12872 Micron Semiconductor Products, mt18vddt12872 Datasheet
mt18vddt12872
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mt18vddt12872 Summary of contents
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... DD18C32_64_128_256x72G.fm - Rev. E 9/04 EN PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. 256MB, 512MB, 1GB, 2GB (x72, ECC, SR) MT18VDDT3272 – 256MB MT18VDDT6472 – 512MB MT18VDDT12872 – 1GB MT18VDDT25672 – 2GB For the latest data sheet, please refer to the Micron site: www.micron.com/products/modules Figure 1: 184-Pin DIMM (MO-206) Standard 1 ...
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... MT18VDDT6472Y-262__ 512MB MT18VDDT6472G-26A__ 512MB MT18VDDT6472Y-26A__ 512MB 512MB MT18VDDT6472G-265__ MT18VDDT6472Y-265__ 512MB MT18VDDT6472G-202__ 512MB MT18VDDT6472Y-202__ 512MB MT18VDDT12872G-262__ MT18VDDT12872Y-262__ MT18VDDT12872G-26A__ MT18VDDT12872Y-26A__ MT18VDDT12872G-265__ MT18VDDT12872Y-265__ MT18VDDT12872G-202__ MT18VDDT12872Y-202__ 2 MT18VDDT25672G-262__ 2 MT18VDDT25672Y-262__ 2 MT18VDDT25672G-26A__ 2 MT18VDDT25672Y-26A__ 2 MT18VDDT25672G-265__ 2 MT18VDDT25672Y-265__ 2 MT18VDDT25672G-202__ 2 MT18VDDT25672Y-202__ NOTE: 1. All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current revision codes ...
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Table 3: Pin Assignment (184-Pin DIMM Front) PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL DQ17 47 REF 2 DQ0 25 DQS2 DQ1 DQS0 ...
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Table 5: Pin Descriptions Pin numbers may not correlate with symbols; refer to Pin Assignment Tables on page 3 for more information PIN NUMBERS SYMBOL 10 63, 65, 154 WE#, CAS#, RAS# 137, 138 CK0, CK0# 21 157 52, 59 ...
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... Input/ Data I/Os: Data bus. Output SCL Input Serial Clock for Presence-Detect: SCL is used to synchronize the presence-detect data transfer to and from the module. Input Presence-Detect Address Inputs: These pins are used to configure the presence-detect device. SDA Input/ Serial Presence-Detect Data: SDA is a bidirectional pin used to ...
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... CKE0 WE# CK CK# NOTE: 1. All resistor values are 22 unless otherwise specified. 2. Per industry standard, Micron utilizes various component speed grades as referenced in the Module Part Numbering Guide at www.micron.com/numberguide. pdf: 09005aef808a331f, source: 09005aef80858037 DD18C32_64_128_256x72G.fm - Rev. E 9/04 EN 256MB, 512MB, 1GB, 2GB (x72, ECC, SR RS0# ...
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... CKE0 WE# CK CK# NOTE: 1. All resistor values are 22 unless otherwise specified. 2. Per industry standard, Micron utilizes various component speed grades as referenced in the Module Part Numbering Guide at www.micron.com/numberguide. pdf: 09005aef808a331f, source: 09005aef80858037 DD18C32_64_128_256x72G.fm - Rev. E 9/04 EN 256MB, 512MB, 1GB, 2GB (x72, ECC, SR RS0# ...
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... General Description The MT18VDDT3272, MT18VDDT12872, and MT18VDDT25672 are high- speed CMOS, dynamic random-access, 512MB, 1GB, and 2GB memory modules organized in x72 (ECC) configuration. DDR SDRAM modules use internally configured quad-bank DDR SDRAM devices. DDR SDRAM modules use a double data rate archi- tecture to achieve high-speed operation ...
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... A2–Ai when the burst length is set to four and by A3–Ai when the burst length is set to eight (where Ai is the most significant column address bit for a given module configuration. See Note 5 of Table 6, Burst Definition Table, on page 10, Burst Definition Table.) The remaining (least significant) address bit(s) is (are) used to select the starting location within the block ...
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Table 6: Burst Definition Table ORDER OF ACCESSES WITHIN STARTING BURST COLUMN TYPE = LENGTH ADDRESS SEQUENTIAL 0 0-1-2 1-2-3 2-3-0 3-0-1 ...
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... DDR SDRAM RDIMM Figure 7: Extended Mode Register Definition Diagram 256MB Module BA1 BA0 A8 A11 A10 Operating Mode 512MB and 1GB Modules A8 BA1 BA0 A12 A11 A10 Operating Mode 2GB Module ...
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Commands Table 8, Commands Truth Table, and Table 9, DM Operation Truth Table, provide a general reference of available commands. For a more detailed description Table 8: Commands Truth Table CKE is HIGH for all commands shown except SELF REFRESH; ...
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Absolute Maximum Ratings Stresses greater than those listed may cause perma- nent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the opera- ...
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Table 12: I Specifications and Conditions – 256MB DD DDR SDRAM components only Notes: 1–5, 8, 10, 12; notes appear on pages 22–25; 0°C PARAMETER/CONDITION OPERATING CURRENT: One device bank; Active-Precharge (MIN (MIN); DQ, DM ...
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Table 13: I Specifications and Conditions – 512MB DD DDR SDRAM components only Notes: 1–5, 8, 10, 12; notes appear on pages 22–25; 0°C PARAMETER/CONDITION OPERATING CURRENT: One device bank; Active-Precharge (MIN (MIN); DQ, DM ...
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I Specifications and Conditions – 1GB DD DDR SDRAM components only Notes: 1–5, 8, 10, 12; notes appear on pages 22–25; 0°C PARAMETER/CONDITION OPERATING CURRENT: One device bank; Active-Precharge (MIN (MIN); DQ, DM and DQS ...
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I Specifications and Conditions – 2GB DD DDR SDRAM components only Notes: 1–5, 8, 10, 12; notes appear on pages 22–25; 0°C PARAMETER/CONDITION OPERATING CURRENT: One device bank; Active-Precharge (MIN (MIN); DQ, DM and DQS ...
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Table 14: Capacitance Note: 11; notes appear on pages 22–25 PARAMETER Input/Output Capacitance: DQ, DQS Input Capacitance: Command and Address, S#, CKE Input Capacitance:CK, CK# Table 15: Electrical Characteristics and Recommended AC Operating Conditions DDR SDRAM Components Only Notes: 1–5, ...
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Table 15: Electrical Characteristics and Recommended AC Operating Conditions (Continued) DDR SDRAM Components Only AC CHARACTERISTICS PARAMETER PRECHARGE command period DQS read preamble DQS read postamble ACTIVE bank a to ACTIVE bank b command DQS write preamble DQS write preamble ...
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Table 16: DDR SDRAM Component Electrical Characteristics and Recommended AC Operating Conditions Notes: 1–5, 12–15, 29; notes appear on pages 22–25; 0°C AC CHARACTERISTICS PARAMETER Access window of DQs from CK/CK# CK high-level width CK low-level width Clock cycle time ...
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Table 16: DDR SDRAM Component Electrical Characteristics and Recommended AC Operating Conditions (Continued) Notes: 1–5, 12–15, 29; notes appear on pages 22–25; 0°C AC CHARACTERISTICS PARAMETER Write recovery time Internal WRITE to READ command delay Data valid output window REFRESH ...
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Notes 1. All voltages referenced Tests for AC timing and electrical AC and DC DD characteristics may be conducted at nominal ref- erence/supply voltage levels, but the related spec- ifications and device operation are ...
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DRAM control- ler greater than eight refresh cycles is not allowed. 22. The valid data window is derived by achieving t t other specifications CK/2 ...
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READs and WRITEs with auto precharge are not t allowed to be issued until RAS (MIN) can be satis- fied prior to the internal precharge command being issued. 32. Any positive glitch in the nominal voltage must be less ...
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... DLL is required to be reset. This is followed by 200 clock cycles (before READ commands). 47. Leakage number reflects the worst case leakage possible through the module pin, not what each memory device contributes. 48. When an input signal is indicated to be HIGH LOW defined as a steady state logic HIGH or ...
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Initialization To ensure device operation the DRAM must be ini- tialized as described below: 1. Simultaneously apply power Apply V and then V power. REF TT 3. Assert and hold CKE at a LVCMOS logic low. 4. ...
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... The timing and switching specifications for the register listed above are critical for proper operation of the DDR SDRAM Registered DIMMs. These are meant subset of the parameters for the specific device used on the module. Detailed information for this register is available in JEDEC Standard JESD82. ...
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... The timing and switching specifications for the PLL listed above are critical for proper operation of the DDR SDRAM Registered DIMMs. These are meant subset of the parameters for the specific device used on the module. Detailed information for this PLL is available in JEDEC Standard JESD82. ...
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... NOTE: 1. Micron Technology, Inc. recommends a minimum air flow of 1 meter/second (~197 LFM) across the module. 2. The component case temperature measurements shown above were obtained experimentally. The typical system to be used for experimental purposes is a dual-processor 600 MHz work station, fully loaded, with four comparable registered memory modules ...
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SPD Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (as shown in Figure 13, Data Validity, and Figure ...
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Table 19: EEPROM Device Select Code The most significant bit (b7) is sent first SELECT CODE Memory Area Select Code (two arrays) Protection Register Select Code Table 20: EEPROM Operating Modes MODE RW BIT Current Address Read Random Address Read ...
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Table 21: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced DDSPD PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic 1; All inputs INPUT LOW VOLTAGE: Logic 0; All inputs OUTPUT LOW VOLTAGE 3mA ...
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... Minimum Row Precharge Time, 28 Minimum Row Active to Row t Active, RRD pdf: 09005aef808a331f, source: 09005aef80858037 DD18C32_64_128_256x72G.fm - Rev. E 9/04 EN 256MB, 512MB, 1GB, 2GB (x72, ECC, SR) ENTRY (VERSION) MT18VDDT3272 MT18VDDT6472 MT18VDDT12872 128 256 SDRAM DDR SSTL 2.5V 7ns (-262/-26A) 7.5ns (-265) ...
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... PCB Identification Code 92 Identification Code (Continued) 93 Year of Manufacture in BCD pdf: 09005aef808a331f, source: 09005aef80858037 DD18C32_64_128_256x72G.fm - Rev. E 9/04 EN 256MB, 512MB, 1GB, 2GB (x72, ECC, SR) ENTRY (VERSION) MT18VDDT3272 MT18VDDT6472 MT18VDDT12872 t 15ns (-262) RCD 20ns (-26A/-265/-202) t RAS 45ns (-262/-26A/-265) 40ns (-202) ...
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... Systems requiring the fast slew rate setup and hold values are supported, provided the faster mini- mum slew rate is met. pdf: 09005aef808a331f, source: 09005aef80858037 DD18C32_64_128_256x72G.fm - Rev. E 9/04 EN 256MB, 512MB, 1GB, 2GB (x72, ECC, SR) 184-PIN DDR SDRAM RDIMM ENTRY (VERSION) MT18VDDT3272 MT18VDDT6472 MT18VDDT12872 Variable Data Variable Data – ...
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... Fundamental Memory Type 3 Number of Row Addresses on Assembly 4 Number of Column Addresses on Assembly 5 Number of Physical Ranks on DIMM 6 Module Data Width 7 Module Data Width (Continued) 8 Module Voltage Interface Levels 9 t SDRAM Cycle Time, CK, (CAS Latency = 2.5) (See note 1) 10 SDRAM Access from Clock,( (CAS Latency = 2.5) ...
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... The value of RAS used for -262/-26A/-265 modules is calculated from 3. The JEDEC SPD specification allows fast or slow slew rate values for these bytes. The worst-case (slow slew rate) value is represented here. Systems requiring the fast slew rate setup and hold values are supported, provided the faster mini- mum slew rate is met ...
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Figure 17: Standard PCB Dimensions U1 U2 0.079 (2.00) R (4X) 0.098 (2.50) D (2X) 0.091 (2.30) TYP. PIN 1 0.050 (1.27) TYP. 0.091 (2.30) TYP. U14 U15 PIN 184 NOTE: All dimensions in inches (millimeters); pdf: 09005aef808a331f, source: 09005aef80858037 ...
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Figure 18: Low Profile PCB Dimensions 0.079 (2.00) R (4X 0.098 (2.50) D (2X) 0.091 (2.30) TYP. PIN 1 0.050 (1.27) TYP. 0.091 (2.30) 2.55 (64.77) TYP. U10 U11 U12 PIN 184 NOTE: All dimensions in inches ...