mt18lsdt12872a Micron Semiconductor Products, mt18lsdt12872a Datasheet - Page 13

• Manufacturer Part Number: mt18lsdt12872a
• Description: Synchronous Dram Module
• Manufacturer: Micron Semiconductor Products

Write Burst Mode
Table 7:
Commands
Table 8:
CKE is HIGH for all commands shown except SELF REFRESH; notes appear following the Truth Table
PDF: 09005aef8088b1bf/Source: 09005aef808807ca
SD9_18C64_128X72AG.fm - Rev. C 6/05 EN
Name (Function)
COMMAND INHIBIT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE
burst)
BURST TERMINATE
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH
(Enter self refresh mode)
LOAD MODE REGISTER
Write Enable/Output Enable
Write Inhibit/Output High-Z
Speed
-13E
-133
CAS Latency Table
Truth Table – SDRAM Commands and DQMB Operation
Notes: 1. A0–A12 provide row address; BA0–BA1 determine which device bank is made active.
When M9 = 0, the burst length programmed via M0–M 2 applies to both READ and
WRITE bursts; when M9 = 1, the programmed burst length applies to READ bursts, but
write accesses are single-location (non burst) accesses.
Table 8 provides a quick reference of available commands. This is followed by a written
description of each command. For a more detailed description of commands and oper-
ations, refer to the 512Mb SDRAM component data sheet.
2. A0–A9, A11 provide column address; A10 HIGH enables the auto-precharge feature (non-
3. A10 LOW: BA0–BA1 determine which device bank is being precharged. A10 HIGH: all
4. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
5. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care”
6. A0–A11 define the op-code written to the mode register and A12 should be driven LOW.
7. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock
persistent), while A10 LOW disables the auto-precharge feature; BA0–BA1 determine
which device bank is being read from or written to.
device banks are precharged and BA0, BA1 are “Don’t Care.”
except for CKE.
delay).
CAS Latency = 2
512MB (SR), 1GB (DR): (x72, ECC) 168-Pin SDRAM UDIMM
≤ 133
≤ 100
Allowable Operating Clock Frequency (MHz)
CS#
H
L
L
L
L
L
L
L
L
–
–
13
RAS# CAS# WE# DQMB
X
H
H
H
H
L
L
L
L
–
–
Micron Technology, Inc., reserves the right to change products or specifications without notice.
X
H
H
H
H
L
L
L
L
–
–
H
H
H
H
X
L
L
L
L
–
–
L/H
L/H
H
X
X
X
X
X
X
X
L
CAS Latency = 3
Bank/Row
Bank/Col
Bank/Col
Op-code
©2002 Micron Technology, Inc. All rights reserved.
ADDR
Code
≤ 143
≤ 133
X
X
X
X
–
–
High-Z
Active
Active
Valid
DQ
Commands
X
X
X
X
X
X
X
Notes
4, 5
1
2
2
3
6
7
7