mt18jsf25672pdy-1g1 Micron Semiconductor Products, mt18jsf25672pdy-1g1 Datasheet - Page 18

• Manufacturer Part Number: mt18jsf25672pdy-1g1
• Description: 2gb X72, Ecc, Dr 240-pin Ddr3 Sdram Rdimm
• Manufacturer: Micron Semiconductor Products

Table 21:
Temperature Format
Temperature Trip Point Registers
Table 22:
Table 23:
Critical Temperature Register
Table 24:
PDF: 09005aef8304aded/Source: 09005aef8304ae2b
JSF18C256x72PD.fm - Rev. A 4/08 EN
15
15
15
0
0
0
Condition
Clears
14
14
14
Sets
0
0
0
Hysteresis
Alarm Temperature Lower Boundary Register (Address: 0x02)
Alarm Temperature Lower Boundary Register (Address: 0x03)
Critical Temperature Register (Address: 0x04)
13
13
13
0
0
0
MSB
MSB
MSB
12
12
12
The temperature trip point registers and temperature readout register use a
“2’s complement” format to enable negative numbers. The least significant bit (LSB) is
equal to 0.0625°C or 0.25°C depending on which register is referenced. As an example,
assuming an LSB of 0.0625°C:
• A value of 0x018C would equal 24.75°C
• A value of 0x06C0 would equal 108°C
• A value of 0x1E74 would equal –24.75°C
The upper and lower temperature boundary registers are used to set the maximum and
minimum values of the alarm window. LSB for these registers is 0.25°C. All RFU bits in
the register will always report zero.
The critical temperature register is used to set the maximum temperature above the
alarm window. The LSB for this register is 0.25°C. All RFU bits in the register will always
report zero.
Temperature
Gradient
11
11
11
Falling
Rising
Below Alarm Window Bit
10
10
10
Alarm window upper boundary temperature
Temperature Sensor with Serial Presence-Detect EEPROM
Alarm window lower boundary temperature
9
9
9
Critical Temperature
Critical temperature trip point
2GB (x72, ECC, DR) 240-Pin DDR3 SDRAM RDIMM
8
8
8
T
L
- Hyst
Bit
Bit
Bit
18
T
L
7
7
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
6
6
6
Temperature
5
5
5
Gradient
Falling
Rising
Above Alarm Window Bit
4
4
4
3
3
3
©2008 Micron Technology, Inc. All rights reserved
Critical Temperature
LSB
LSB
LSB
2
2
2
T
H
T
- Hyst
RFU
RFU
RFU
H
1
1
1
RFU
RFU
RFU
0
0
0