mt18jsf25672py-1g1 Micron Semiconductor Products, mt18jsf25672py-1g1 Datasheet - Page 4

• Manufacturer Part Number: mt18jsf25672py-1g1
• Description: 2gb X72, Ecc, Sr 240-pin Ddr3 Sdram Rdimm
• Manufacturer: Micron Semiconductor Products

Table 6:
PDF: 09005aef8303ca34/Source: 09005aef8303ca7a
JSF18C256x72P.fm - Rev. A 4/08 EN
RAS#, CAS#, WE#
DQS#[17:0]
DQS[17:0],
CK0, CK0#
E
DQ[63:0]
Symbol
EVENT#
A[15:0]
BA[2:0]
RESET#
SA[2:0]
CB[7:0]
RR
P
ODT0
CKE0
SDA
AR
S0#
SCL
_O
_I
UT
N
#
Pin Descriptions
(open drain)
(open drain)
(LVCMOS)
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Type
I/O
I/O
I/O
I/O
Description
Address inputs: Provide the row address for ACTIVATE commands, and the column
address and auto precharge bit (A10) for READ/WRITE commands, to select one location
out of the memory array in the respective bank. A10 is sampled during a PRECHARGE
command to determine whether the PRECHARGE applies to one bank (A10 LOW, bank
selected by BA[2:0]) or all banks (A10 HIGH). If only one bank is to be precharged, the
bank is selected by BA. A12 is also used for BC4/BL8 identification as “BL on-the-fly”
during CAS commands. The address inputs also provide the op-code during the mode
register command set
calculate parity on the command/address bus.
Bank address inputs: BA[2:0] define the device bank to which an ACTIVATE, READ,
WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode register
(MR0, MR1, MR2, and MR3) is loaded during the LOAD MODE command. BA[1:0] are
used as part of the parity calculation.
Clock: CK and CK# are differential clock inputs. All control, command, and address
input signals are sampled on the crossing of the positive edge of CK and the negative
edge of CK#.
Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal
circuitry and clocks on the DRAM.
On-die termination: ODT enables (registered HIGH) and disables (registered LOW)
termination resistance internal to the DRAM. When enabled in normal operation, ODT is
only applied to the following pins: DQ, DQS, DQS#, and DM. The ODT input will be
ignored if disabled via the LOAD MODE command.
Parity input: Parity bit for the address, RAS#, CAS#, and WE#.
Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being
entered.
Reset: RESET# is an active LOW CMOS input referenced to V
receiver is a CMOS input defined as a rail-to-rail signal with DC HIGH ≥ 0.8 × V
LOW ≤ 0.2 × V
applications will most likely be unterminated, heavily loaded, and have very slow slew
rates. A slow slew rate receiver design is recommended along with implementing on-
chip noise filtering to prevent false triggering (RESET# assertion minimum pulse width is
100ns).
Chip select: S# enables (registered LOW) and disables (registered HIGH) the command
decoder.
Serial address inputs: These pins are used to configure the temperature sensor/SPD
EEPROM address range on the I
Serial clock for temperature sensor/SPD EEPROM: SCL is used to synchronize
communication to and from the temperature sensor/SPD EEPROM.
Check bits: Data used for ECC.
Data input/output: Bidirectional data bus.
Data strobe: DQS and DQS# are differential data strobes. Output with read data. Edge-
aligned with read data. Input with write data. Center-aligned with write data.
Serial data: SDA is a bidirectional pin used to transfer addresses and data into and out
of the temperature sensor/SPD EEPROM on the module on the I
Parity error output: Parity error found on the command and address bus.
Temperature event: The EVENT# pin is asserted by the temperature sensor when
critical temperature thresholds have been exceeded.
DD
. RESET# assertion and deassertion are asynchronous. System
2GB (x72, ECC, SR) 240-Pin DDR3 SDRAM RDIMM
.
A[13:0] address the 1Gb DDR3 devices. A[15:14] are needed to
4
2
C bus.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Pin Assignments and Descriptions
SS
©2008 Micron Technology, Inc. All rights reserved
. The RESET# input
2
C bus.
DD
and DC