gs8321e36e-250v GSI Technology, gs8321e36e-250v Datasheet - Page 7

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gs8321e36e-250v

Manufacturer Part Number
gs8321e36e-250v
Description
2m X 18, 1m X 32, 1m X 36 36mb Sync Burst Srams
Manufacturer
GSI Technology
Datasheet
Mode Pin Functions
Note:
There is a pull-down device on the ZZ pin, so this input pin can be unconnected and the chip will operate in the default states as specified in the
above table.
There is a pull-up device on the FT pin and a pull-down device on the ZZ pin, so this input pin can be unconnected and the chip will operate in
the default states as specified in the above table.
Burst Counter Sequences
Linear Burst Sequence
Note:
The burst counter wraps to initial state on the 5th clock.
Rev: 1.05a 12/2007
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
2nd address
3rd address
1st address
4th address
Output Register Control
Power Down Control
Burst Order Control
Mode Name
A[1:0] A[1:0] A[1:0] A[1:0]
00
01
10
11
01
10
00
11
10
11
00
01
00
01
10
11
Pin Name
7/31
LBO
ZZ
FT
Interleaved Burst Sequence
Note:
The burst counter wraps to initial state on the 5th clock.
2nd address
3rd address
4th address
1st address
H or NC
L or NC
State
H
H
L
L
A[1:0] A[1:0] A[1:0] A[1:0]
00
01
10
11
01
00
11
10
Standby, I
GS8321E18/32/36E-xxxV
Interleaved Burst
Flow Through
Linear Burst
Function
Pipeline
Active
10
00
01
11
DD
© 2003, GSI Technology
= I
SB
11
10
01
00
BPR 1999.05.18

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