at78c1501 ATMEL Corporation, at78c1501 Datasheet - Page 5

• Manufacturer Part Number: at78c1501
• Description: Dvd / Cd Atapi Controller
• Manufacturer: ATMEL Corporation

ATAPI Interface
Table 2. ATAPI Interface I/O Pin List
2049A–DVD–07/02
Pin Name
CS0-
CS1-
DD[15]
DD[14]
DD[13]
DD[12]
DD[11]
DD[10]
DD[9]
DD[8]
DD[7]
DD[6]
DD[5]
DD[4]
DD[3]
DD[2]
DD[1]
DD[0]
DASP-
DA[2]
DA[1]
DA[0]
DMACK-
DMARQ-
INTRQ
Pin #
205
204
203
206
207
13
15
17
19
22
24
26
28
29
27
25
23
20
18
16
14
11
3
5
4
Pin Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
I
I
I
I
The AT78C1501 supports the ATAPI CD-ROM specification (IDE CD-ROM Interface)
and can drive IDE signals directly. The host interface contains a 12-byte command
packet FIFO and IDE registers for transferring command and status data. The host inter-
face also contains a data FIFO for transferring data from buffer DRAM to the host. The
host interface contains the following pins:
Pin Description
Device Chip Select 0: Chip select signal from host to select the Command Block registers.
Device Chip Select 1: Chip select signal from host to select the Command Block registers.
Device Data Bus: Bidirectional data bus between the host and the device. The lower eight
bits are used for 8-bit register transfers. Data transfers are 16 bits wide.
Device Active or Slave Present: This is a time-multiplexed signal that indicates that a device
is active or that Device 1 is present.
Device Address: This is the 3-bit binary coded address asserted by the host to access a
register or data port in the device.
DMA Acknowledge: This signal shall be used by the host in response to DMARQ- to initiate
DMA transfers.
DMA Request: This signal, used for DMA data transfers between the host and device, shall
be asserted by the device when it is ready to transfer data to or from the host. The direction
of data transfer is controlled by DIOR- and DIOW-. This signal is used in a handshake
manner with DMACK, i.e., the device shall wait until the host asserts DMACK, before
negating DMARQ and reasserting DMARQ, if there is more data to transfer.
Device Interrupt: This signal is used by the selected device to interrupt the host system.
When the nIEN bit is cleared to “0” and the device is selected, INTRQ shall be enabled
through a tristate buffer. When the nIEN bit is set to “1” or the device is not selected, the
INTRQ signal shall be in a high impedance state.
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