ne56632-xx NXP Semiconductors, ne56632-xx Datasheet - Page 9

• Manufacturer Part Number: ne56632-xx
• Description: Active-low System Reset With Adjustable Delay Time
• Manufacturer: NXP Semiconductors

Philips Semiconductors
TECHNICAL DISCUSSION
The NE56632-XX is a bipolar IC designed to provide power source
monitoring and a system reset function in the event the power sags
below an acceptable level for the system to operate reliably. The
reset threshold incorporates a typical hysteresis of 50 mV to prevent
erratic reasserts from being generated. An internal delay time circuit
provides a adjustable power-on reset delay of typically 200 s to
200 ms using an external capacitor.
The output of the NE56632-XX utilizes an open collector topology,
which requires an external pull-up resistor to V
be regarded as a disadvantage, it is advantageous in many
sensitive applications. Because the open collector output cannot
source reset current when both are operated from a common supply,
the NE56632-XX offers a safe interconnect to a wide variety of
microprocessors.
The NE56632-XX operates at low supply currents, typically 3 A,
while offering precision threshold detection ( 1.5%).
Figure 22 is a functional block diagram of the NE56632-XX. The
internal reference source voltage, V
temperature range. The reference voltage is connected to the
non-inverting inputs of the threshold Comparator 1 and
Comparator 2, while the inverting input of Comparator 1 monitors
the supply voltage through a voltage divider (R1 and R2). The output
of the comparator drives the series base resistor, R3 of a common
emitter amplifier, Q1. The collector of Q1 is connected to the
inverting terminal of Comparator 2. The output of Comparator 2 is
connected to the series base resistor, R4 of the output common
emitter transistor, Q2. The open collector output of Q2 provides the
reset output.
The Delay Time Control is outputted at the junction of the collector
of Q1 and the inverting input of Comparator 2. The reset release
time delay, t
show t
When the supply voltage sags to the threshold detection voltage, the
resistor divider network supplies a voltage to the inverting terminal of
2003 Oct 14
Active-LOW system reset with adjustable delay time
PLH
as a function of the external delay capacitor, C
PLH
is set with an external capacitor. Figures 25 and 26
V
CC
REF
5
,
is typically 0.65 V over the
V
REF
CC
. Though this may
Figure 22. Functional diagram.
R1
R2
D
.
COMP1
R3
I
9
D
Q1
the threshold comparator which is less than V
of the comparator to go to a HIGH state. This causes the common
emitter amplifier, Q1 to turn ON pulling down the non-inverting
terminal of Comparator 2 which causes its output to go to a HIGH
state. This HIGH output level turns on the output common emitter
transistor, Q2. The collector output of Q2 is pulled LOW through the
external pull-up resistor, thereby asserting the Active-LOW reset.
Threshold hysteresis is established by turning on the bipolar common
emitter transistor, Q1 when the input threshold Comparator 1 goes
to a HIGH state. This occurs when V
threshold level. With the output of Q1 connected to the non-inverting
terminal of Comparator 2, the non-inverting terminal has a level near
ground at about 0.4 V when the reset is asserted (Active-LOW). For
the Comparator 2 to reverse its output, the Comparator 1 output and
Q1 must overcome the additional pull-down voltage present on the
inverting input of Comparator 2. The differential voltage required to
do this establishes the hysteresis voltage of the sensed threshold
voltage. Typically, it is 50 mV.
When V
device will assert a Reset LOW output at or near ground potential.
As V
released and the output follows V
from (V
Hysteresis voltage = Release voltage – Detection Threshold voltage
where:
When V
0.65 V, the output is undefined and the output reset low assertion is
no longer guaranteed. At this level of V
V
zero.
TC
1
CC
V
V
V
. As V
CC
hys
SH
SL
CC
= V
CC
rises from (V
= V
CC
= V
COMP2
CC
> V
sags, and it is below the detection Threshold (V
SH
drops below the minimum operating voltage, typically
SL
SH
drops even further to zero, V
SL
+ V
– V
– V
R4
) to V
hys
hys
SL
SL01607
Q2
CC
SL
(SUBSTRATE)
< V
will cause the output to be pulled to ground.
4
3
2
SL
) to V
V
GND
SUB
OUT
CC
SH
. Conversely, decreases in V
CC
or higher, the Reset is
CC
sags to or below the
the output will try to rise to
OUT
NE56632-XX
REF
reset also goes to
, causing the output
Product data
SL
), the
CC