lis3l02ds STMicroelectronics, lis3l02ds Datasheet - Page 8

• Manufacturer Part Number: lis3l02ds
• Description: Three Axis 2g-6g Linear Accelerometer
• Manufacturer: STMicroelectronics

LIS3L02DS
knowledge pulse. The receiver must then pull the data line LOW so that it remains stable low during the
HIGH period of the acknowledge clock pulse. A receiver which has been addressed is obliged to generate
an acknowledge after each byte of data has been received.
The I
be adhered to. After the start condition (ST) a salve address is sent, once a slave acknowledge has been
returned, a 8-bit sub-address will be transmitted: the 7 LSB represent the actual register address while the
MSB enables address autoincrement. If the MSB of the SUB field is 1, the SUB (register address) will be
automatically incremented to allow multiple data read/write.
If the LSB of the slave address was ‘1’ (read), a repeated START condition will have to be issued after the
two sub-address bytes; if the LSB is ‘0’ (write) the Master will transmit to the slave with direction un-
changed.
Transfer when Master is writing one byte to slave
Transfer when Master is writing multiple bytes to slave:
Transfer when Master is receiving (reading) one byte of data from slave:
Transfer when Master is receiving (reading) multiple bytes of data from slave
Data are transmitted in byte format. Each data transfer contains 8 bits. The number of bytes transferred
per transfer is unlimited. Data is transferred with the Most Significant Bit (MSB) first. If a receiver can’t re-
ceive another complete byte of data until it has performed some other function, it can hold the clock line,
SCL LOW to force the transmitter into a wait state. Data transfer only continues when the receiver is ready
for another byte and releases the data line. If a slave receiver doesn’t acknowledge the slave address (i.e.
it is not able to receive because it is performing some real time function) the data line must be left HIGH
by the slave. The Master can then abort the transfer. A LOW to HIGH transition on the SDA line while the
SCL line is HIGH is defined as a STOP condition. Each data transfer must be terminated by the generation
of a STOP condition.
In order to read multiple bytes, it is necessary to assert the most significant bit of the sub-address field. In
other words, SUB(7) must be equal to 1 while SUB(6-0) represents the address of first register to read.
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Master
Slave
2
Master
Slave
C embedded inside the Gengine ASIC behaves like a slave device and the following protocol must
Master
Slave
ST
ST
Master
Slave
ST
SAD + W
SAD + W
SAD + W
Master
Slave
ST
SAK
SAD + W
SAK
SR
SAK
SUB
DATA
SUB
SUB
SAK
SAK
SAK
MAK
SAK
SUB
SR
SR
DATA
DATA
SAK
SAD + R
SAD + R
NMAK
DATA
SAK
SAK
SAK
DATA
SP
SAK
DATA
DATA
SP
SAK
NMAK
MAK
SP
SP