w66910 Winbond Electronics Corp America, w66910 Datasheet - Page 45

• Manufacturer Part Number: w66910
• Description: Te Mode Isdn S/t-controller With Microprocessor Interface
• Manufacturer: Winbond Electronics Corp America

8.1.3 D_ch command register
Value after reset: 00H
RACK Receive Acknowledge
After a D_RMR or D_RME interrupt, the processor must read out the data in D_RFIFO and then sets this bit to acknowledge the
interrupt. Writing “0” to this bit has no effect.
RRST Receiver Reset
Setting this bit resets the D_ch HDLC receiver and clears the D_RFIFO data. Writing “0” to this bit has no effect.
STT1 Start Timer 1
The timer 1 is started when this bit is set to one. The timer is stopped when it expires or by a write of the TIMR1 register.
Writing “0” to this bit has no effect.
XMS Transmit Message Start/Continue
Setting this bit will start or continue the transmission of a frame. The opening flag is automatically added by the HDLC
controller. Writing “0” to this bit has no effect.
XME Transmit Message End
Setting this bit indicates the end of frame transmission.. The D_ch HDLC controller automatically appends the CRC and the
closing flag after the data transmission. Writing “0” to this bit has no effect.
Note: If the frame
XRST Transmitter Reset
Setting this bit resets the D_ch HDLC transmitter and clears the D_XFIFO. The transmitter will send inter frame time fill pattern
(which is 1's) immediately. This command also results in a transmit FIFO ready condition. Writing “0” to this bit has no effect.
8.1.4 D_ch Mode Register D_MODE
Value after reset : 00H
RACT Receiver Active
RACK
7
7
0
RACT
RRST
6
6
64 bytes, XME plus XMS commands must be issued at the same time.
XACTB
5
0
5
STT1
4
4
0
XMS
D_CMDR
3
3
0
Read/Write Address 03H
MFD
2
0
2
-45 -
Write
XME
DLP
1
1
XRST
RLP
0
0
Address 02H
W66910 PCI ISDN S/T-Controller
Publication Release Date:
Data Sheet
Revision 1.0
Feb,2001