w6694 Winbond Electronics Corp America, w6694 Datasheet - Page 14

• Manufacturer Part Number: w6694
• Description: Usb Bus Isdn S/t-controller
• Manufacturer: Winbond Electronics Corp America

Contents of address byte:
The data byte is the write data (write operation) or 00h (read operation).
7.1.4 Bulk-IN Transaction (Endpoint 2)
Bulk-IN endpoint is for retrieving register data of W6694. It returns the registers data that are
requested by most recent Bulk-OUT data-read request. Inside the data packet, one register occupies
2 bytes. The first is register’s offset address, the 2
be sent to host in one Bulk-IN packet.
7.1.5 Interrupt-IN Transaction (Endpoint 3)
Interrupt-IN endpoint is used to periodically poll device interrupt data. W6694 use this endpoint to
report interrupt status of all interrupt sources. All four bytes data of interrupt registers will be sent to
host if ISTA is not 0. If no interrupt is detected by W6694 when received Interrupt-IN token, A NAK
token will return to the USB host.
Data packet for Interrupt-IN transaction:
7.1.6 Isochronous-OUT Transaction (Endpoint 4)
After power-on or hardware reset, all B and D channels transmit FIFO (XFIFO) are disabled. A
disabled XFIFO can not receive data from USB. But the transmitter will automatically send inter
frame time fill pattern (all 1’s) to ISDN interface. The disabled XFIFO can be enabled by command
XEN on each channel. An enabled XFIFO can receive data from USB, and send data to the USB
host.
Software decides the size of data to transmit depending on available XFIFO space, which is indicated
by XFR flag carried by Isochronous-IN packet. When XFR is reported to host, it means that XFIFO
has at least half of the total XFIFO size available for that channel. Each channel has its own XFIFO
and status flags.
If the incoming Isochronous-OUT packet is detected error, some action will be automatically taken for
D and B channel XFIFO. For D channel, the XFIFO is reset and automatically enabled. For B
channel, the XFIFO are not reset, and the data remained in XFIFO are still valid and will be
transmitted to ISDN later. But the new incoming B channel data will be replaced by FFh, and stored
Bit 7:
Bit 4-0:
Offset 0
address
Offset 0
ISTA
Bit 7
0/1
1
0/1 = Read/Write
Address offset of register.
data1
CIR
1
6
0
1
address
PICR
0
2
2
2
5
PDATA
data2
A4
3
4
3
- 14 -
address
MOIR
nd
A3
4
3
4
3
byte is date. A maximum of 4 register data can
data3
A2
2
5
Preliminary W6694
address
A1
1
6
4
data4
A0
0
7