rsc-464 ETC-unknow, rsc-464 Datasheet - Page 10

• Manufacturer Part Number: rsc-464
• Description: Speech Recognition Processor
• Manufacturer: ETC-unknow

RSC-464
Mapping of logical addresses 080H-0BFH (“bank” register FC is used)
register FC [4:0]
00H (Bank 0)
01H (Bank 1)
02H (Bank 2)
03H (Bank 3)
04H (Bank 4)
05H (Bank 5)
06H (Bank 6)
07H (Bank 7)
NOTE: If a value other than those indicated above is used in the “bank” register, an undefined state will result.
User RAM is assigned both in directly addressed register RAM space and in banked register RAM space.
Addresses 03AH-07FH (70 bytes) of directly addressed register RAM and Banks 0, A and B (192 bytes) of banked
register RAM are assigned for a total of 262 bytes of User RAM.
See the “Special Functions Registers Summary” for details on the contents of SFRs.
L1 Vector Accelerator/Multiplier
A variety of macros are provided by Sensory that manipulate the L1 Vector Accelerator to provide signed and
unsigned multiplication functions. See the “FluentChip™ Technology Library Manual” for information on these
macros and their application.
The L1/Multiplier unit may be independently powered down by programming the register D6.Bit 4 to “0” (“clkExt”
register, “L1clk_on” bit).
Digital Filter
The RSC-464 has a Digital Filter engine capable of dividing up a frequency range into several smaller ranges. It is
also capable of reporting characteristics of each range to the RSC-464 processor. The configuration of the Digital
Filter engine and access to signal characteristics generated are enabled by technology modules that are available
from Sensory “Technology Support” upon request.
Power and Wakeup Control
The typical Active Supply Current is realized when operating with a main clock rate of 14.32 MHz at 3V and all I/O
configured to the high-Z state. Lowering clock frequency reduces active power consumption, although FluentChip™
technology typically requires a 14.32 MHz clock.
Two supply current power-down modes are available – Sleep and Idle modes. In Sleep mode everything is
stopped, and only an I/O event can initiate a wake-up. In Idle mode OSC2 and Timer2 continue to run, and an
Audio Wakeup, I/O Wakeup or Timer2 interrupt request caused by overflow can generate a wake-up.
Sleep mode is entered by setting register E8.Bit7=1 (“ckCtl” register; “pdn” bit), register E8.Bit0=1 (“osc1_off”) and
register E8.Bit1=0 (OSC2 off). Idle mode is entered by setting register E8.Bit7=1, register E8.Bit1=1 (“osc2_on”)
and register E8.Bit0=1. Setting register E8.Bit7=1 (“pdn”) freezes the processor, but does not insure that the DAC,
Audio Wakeup, and the PWM are placed in the lowest possible current-consumption state. Software control must
power these blocks down prior to setting “pdn” to “1”, according to the procedures indicated in “DAC”, “Audio
Wakeup”, and “Pulse Width Modulator Analog Output” Sections. The “FluentChip™ Technology Library Manual”
provides sample code for achieving the lowest current-consumption state for Sleep and Idle modes. The state of
“pdn” bit may be observed externally on the PDN pin (see pin definitions in “Package Options” section) and used to
control power down of circuitry external to the RSC-464, if desired.
NOTE: GPIO (Ports 0 & 2) should be put in input mode and a known state (e.g. light pull-up) whenever possible to
conserve power, and especially in powerdown mode to achieve the specified minimum supply current consumption.
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Physical Bank RAM
00-3FH
40-7FH
80-BFH
C0-FFH
100-13FH
140-17FH
180-1BFH
1C0-1FFH
register FC [4:0]
08H (Bank 8)
09H (Bank 9)
0AH (Bank A)
0BH (Bank B)
0CH
0DH
0EH
0FH
P/N 80-0282-A
Physical Bank RAM
200-23FH
240-27FH
280-2BFH
2C0-2FFH
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Preliminary Data Sheet
© 2005 Sensory Inc.