msm5839cgs-l2 Oki Semiconductor, msm5839cgs-l2 Datasheet - Page 6

• Manufacturer Part Number: msm5839cgs-l2
• Description: Msm5839c Lcd Segment Driver
• Manufacturer: Oki Semiconductor

¡ Semiconductor
FUNCTIONAL DESCRIPTION
Pin Functional Description
• DI
• CP
• DO
• DI
• DO
• DF
• V
• V
• LOAD
The data input pin for the 20-bit shift register (from 1st to 20th bit). The display data is input
to the data input pin in synchronization with a clock pulse.
Clock pulse input pin for the two 20-bit shift registers. The data is shifted in the two 20-bit shift
registers at the falling edge of the clock pulse. Data setup time (t
(t
The 20th output bit of the shift register.
The data which is input from DI
register (20). A 40-bit shift register can be configured by connecting the output of this pin to DI
pin.
The data input pin for the 20-bit shift register (from 21st to 40th bit).
Connecting the DO
The 40th output bit of the shift register.
The data which is input from DI
shift register.
When increasing the number of characters, this pin is used to cascade connect the next
MSM5839C.
Alternate signal input pin for LCD driving waveform.
Supply voltage pins. V
V
Bias supply voltage pins to drive the LCD. Bias voltage is supplied from an external source.
The signal for latching the shift register contents is input from this pin.
When LOAD pin is set at "H", the shift register contents are transferred to the 40-bit 4-level
driver. When LOAD pin is set at "L", the last display output data (O
transferred when LOAD pin was at "H", is held.
DD
2
HOLD
SS
1
21
, V
20
40
(V
is a ground pin (V
3
1
, V
) are required between DI
), V
EE
SS
(V
4
)
20
pin and this pin allows the device to be used as a 40-bit shift register.
SS
DD
= 0V).
should be 4.5 to 5.5V.
1
1
1
is clocked out with a delay of the number of bits of the shift
, DI
is clocked out with a delay of the number of the bits of the
21
and CP.
SETUP
1
) and data hold time
to O
40
), which was
MSM5839C
6/9
21