ep610i-15 Altera Corporation, ep610i-15 Datasheet - Page 19

• Manufacturer Part Number: ep610i-15
• Description: Epld Family
• Manufacturer: Altera Corporation

Altera Corporation
Notes to tables:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
t
t
t
t
t
t
t
t
t
t
t
t
Symbol
IN
IO
LAD
OD
ZX
XZ
SU
H
IC
ICS
FD
CLR
Table 11. EP610-25, EP610-30 & EP610-35 Internal Timing Parameters
These values are specified in
See
timing parameters.
The non-Turbo adder must be added to this parameter when the Turbo Bit option is off.
Sample-tested only for an output change of 500 mV.
The f
Measured with a device programmed as a 16-bit counter.
Sample-tested only. This parameter is a guideline based on extensive device characterization. This parameter
applies for both global and array clocking.
Application Note 78 (Understanding MAX 5000 & Classic Timing)
MAX
Input pad and buffer delay
I/O input pad and buffer delay
Logic array delay
Output buffer and pad delay
Output buffer enable delay
Output buffer disable delay
Register setup time
Register hold time
Array clock delay
Global clock delay
Feedback delay
Register clear time
values represent the highest frequency for pipelined data.
Parameter
Table 3 on page
C1 = 35 pF
C1 = 35 pF
C1 = 5 pF
Condition
758.
Min
11.0
10.0
EP610-25
in this data book for information on internal
Max
11.0
13.0
13.0
8.0
2.0
6.0
6.0
6.0
1.0
3.0
Min
11.0
10.0
EP610-30
Classic EPLD Family Data Sheet
Max
14.0
16.0
16.0
9.0
2.0
7.0
7.0
7.0
1.0
5.0
Min
12.0
10.0
EP610-35
Max
11.0
15.0
17.0
17.0
2.0
9.0
9.0
9.0
0.0
8.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
763