m28f008 Intel Corporation, m28f008 Datasheet - Page 6

• Manufacturer Part Number: m28f008
• Description: 8 Mbit 1 Mbit X 8 Flash Memory
• Manufacturer: Intel Corporation

M28F008
erase and byte write circuitry Write cycles also inter-
nally latch addresses and data needed for byte write
or block erase operations With the appropriate com-
mand written to the register standard microproces-
sor read timings output array data access the intelli-
gent identifier codes or output byte write and block
erase status for verification
Interface software to initiate and poll progress of in-
ternal byte write and block erase can be stored in
any of the M28F008 blocks This code is copied to
and executed from system RAM during actual flash
memory update After successful completion of byte
write and or block erase code data reads from the
M28F008 are again possible via the Read Array
command Erase suspend resume capability allows
system software to suspend block erase to read
data and execute code from any other block
6
FFFFF
EFFFF
DFFFF
CFFFF
BFFFF
AFFFF
E0000
D0000
C0000
B0000
A0000
9FFFF
8FFFF
7FFFF
6FFFF
5FFFF
4FFFF
3FFFF
2FFFF
1FFFF
0FFFF
F0000
90000
80000
70000
60000
50000
40000
30000
20000
10000
00000
Figure 4 Memory Map
64 Kbyte Block
64 Kbyte Block
64 Kbyte Block
64 Kbyte Block
64 Kbyte Block
64 Kbyte Block
64 Kbyte Block
64 Kbyte Block
64 Kbyte Block
64 Kbyte Block
64 Kbyte Block
64 Kbyte Block
64 Kbyte Block
64 Kbyte Block
64 Kbyte Block
64 Kbyte Block
Command User Interface and Write
Automation
An on-chip state machine controls block erase and
byte write freeing the system processor for other
tasks After receiving the Erase Setup and Erase
Confirm commands the state machine controls
block pre-conditioning and erase returning progress
via the Status Register and RY BY output Byte
write is similarly controlled after destination address
and expected data are supplied The program and
erase algorithms of past Intel Flash memories are
now regulated by the state machine including pulse
repetition where required and internal verification
and margining of data
Data Protection
Depending on the application the system designer
may choose to make the V
ble (available only when memory byte writes block
erases are required) or hardwired to V
V
The M28F008 Command User Interface architecture
provides protection from unwanted byte write or
block erase operations even when high voltage is
applied to V
abled whenever V
age V
commodates either design practice and encourages
optimization of the processor-memory interface
The two-step byte write block erase Command User
Interface write sequence provides additional soft-
ware write protection
BUS OPERATION
Flash memory reads erases and writes in-system
via the local CPU All bus cycles to or from the flash
memory conform to standard microprocessor bus
cycles
Read
The M28F008 has three read modes The memory
can be read from any of its blocks and information
can be read from the intelligent identifier or Status
Register V
The first task is to write the appropriate read mode
command to the Command User Interface (array in-
telligent identifier or Status Register) The M28F008
automatically resets to Read Array mode upon initial
device powerup or after exit from deep powerdown
The M28F008 has four control pins two of which
PP
e
LKO
V
PPL
PP
or when RP is at V
PP
can be at either V
memory contents cannot be altered
Additionally all functions are dis-
CC
is below the write lockout volt-
PP
power supply switcha-
IL
PPL
The M28F008 ac-
or V
PPH
PPH
When