ql4058-0pq240m QuickLogic Corp, ql4058-0pq240m Datasheet

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ql4058-0pq240m

Manufacturer Part Number
ql4058-0pq240m
Description
Quickram Esp Combining Performance, Density And Embedded Ram
Manufacturer
QuickLogic Corp
Datasheet
Device Highlights
High Performance & High Density
• Up to 90,000 usable PLD gates with up to
• 300 MHz 16-bit counters, 400 MHz datapaths,
• 0.35 µm four-layer metal non-volatile CMOS
High Speed Embedded SRAM
• Up to 22 dual-port RAM modules, organized in
• 5 ns access times, each port independently
• Fast and efficient for FIFO, RAM, and ROM
Easy to Use/Fast Development
Cycles
• 100% routable with 100% utilization and
• Variable-grain logic cells provide high
• Comprehensive design tools include high quality
Advanced I/O Capabilities
• Interfaces with 3.3 V and 5.0 V devices
• PCI compliant with 3.3 V and 5.0 V busses for
• Full JTAG boundary scan
• I/O cells with individually controlled registered
© 2007 QuickLogic Corporation
316 I/Os
160+ MHz FIFOs
process
user-configurable 1,152 bit blocks
accessible
functions
complete pin-out stability
performance and 100% utilization
Verilog/VHDL synthesis
-1/-2/-3/-4 speed grades
input path and output enables
QuickRAM Family Data Sheet
• • • • • •
QuickRAM ESP Combining Performance, Density and
Embedded RAM
Up to 316 I/O Pins
• Up to 308 bi-directional input/output pins,
• Eight high-drive input/distributed network pins
Eight Low-Skew Distributed
Networks
• Two array clock/control networks are available to
• Six global clock/control networks available to the
High Performance Silicon
• Input + logic cell + output total delays under 6 ns
• Data path speeds over 400 MHz
• Counter speeds over 300 MHz
• FIFO speeds over 160+ MHz
Blocks
PCI-compliant for 5.0 V and 3.3 V buses for
-1/-2/-3/-4 speed grades
the logic cell flip-flop; clock, set, and reset inputs
— each can be driven by an input-only pin
logic cell; F1, clock, set, and reset inputs and the
data input, I/O register clock, reset, and enable
inputs as well as the output enable control—each
can be driven by an input-only, I/O pin, any logic
cell output, or I/O cell feedback
RAM
22
Figure 1: QuickRAM Block Diagram
www.quicklogic.com
Hi gh Speed
Logic Cells
Interface
1,584
1

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ql4058-0pq240m Summary of contents

Page 1

... PCI compliant with 3.3 V and 5.0 V busses for -1/-2/-3/-4 speed grades • Full JTAG boundary scan • I/O cells with individually controlled registered input path and output enables © 2007 QuickLogic Corporation Up to 316 I/O Pins • 308 bi-directional input/output pins, PCI-compliant for 5.0 V and 3.3 V buses for -1/-2/-3/-4 speed grades • ...

Page 2

... Table 2: Max I/O per Device/Package Combination 100 144 208 TQFP TQFP PQFP 110 - - 110 166 - - 166 - - 166 QL4036 QL4058 97,128 131,328 672 1,008 876 1,260 196 244 14 18 16,128 20,736 - - 144 - 208 208/240 256 456 - - 240 ...

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... QuickRAM device and 44 bits wide in the largest device. WDATA WADDR WDATA © 2007 QuickLogic Corporation 2). With a maximum of 308 I/Os, the Figure Figure 2: QuickRAM Module WA RE ...

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... Each cell has a fan- including register and control lines (see Figure 4). • • 4 www.quicklogic.com • • • • TM packages provides a solution for designers who Figure 4: QuickRAM Logic Cell © 2007 QuickLogic Corporation ...

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... WE Hold Time to WCLK HWE t WCLK to RD (WA=RA) WCRD a. Stated timing for worst case Propagation Delay over process variation at V Delay Factor, K, for speed grade, voltage and temperature settings as specified in the Operating Range. © 2007 QuickLogic Corporation = 3 25° 1.00 Table 12 Table 3: Logic Cell ...

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... Propagation Delays (ns) Fanout 1.0 1.0 1.0 1.0 0.0 0.0 0.0 0.0 1.0 1.0 1.0 1.0 0.0 0.0 0.0 0.0 4.0 4.3 4.6 4.9 ° = 3.3 V and Multiply by the appropriate CC A Propagation Delays (ns) Fanout 3.0 3.3 3.6 3.9 ° = 3.3 V and Multiply by the appropriate CC A Propagation Delays (ns) Fanout 1.5 1.6 1.8 1.9 2.4 1.6 1.7 1.9 2.0 2.5 3.1 3.1 3.1 3.1 3.1 0.0 0.0 0.0 0.0 0.0 0.7 0.8 1.0 1.1 1.6 0.6 0.7 0.9 1.0 1.5 2.3 2.3 2.3 2.3 2.3 0.0 0.0 0.0 0.0 0.0 ° = 3.3 V and Multiply by the appropriate CC A Table 12 . © 2007 QuickLogic Corporation 5 1.0 0.0 1.0 0.0 6 2.9 4.4 3.0 4.5 3.1 3.1 0.0 0.0 2.1 3.6 2.0 3.5 2.3 2.3 0.0 0.0 ...

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... Output Delay High to Tri-state PHZ t Output Delay High to Tri-state PLZ Figure 5 a. The loads presented in are used for t © 2007 QuickLogic Corporation Table 8: Clock Cells Parameter Array Clock Delay Table 9: I/O Cell Input Delays Parameter Input Register Hold Time Input Register Clock to Q ...

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... Min. Max. 0 CCIO -0.5 0.3 V 2 0.45 0 GND - GND - -15 -180 40 210 CC or GND 0.50 (typ 100 © 2007 QuickLogic Corporation Unit 3 °C - °C n/a n/a n/a n/a n/a Units + 0 µA µ µA ...

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... Kv and Kt Graphs 1.1000 1.0800 1.0600 1.0400 1.0200 1.0000 0.9800 0.9600 0.9400 0.9200 Figure 7: Temperature Factor vs. Operating Temperature -60 © 2007 QuickLogic Corporation Figure 6: Voltage Factor vs. Supply Voltage Voltage Factor vs. Supply Voltage 3 3.1 3.2 3.3 Supply Voltage (V) Temperature Factor vs. Operating Temperature 1.15 1.10 1.05 1.00 0.95 0.90 0.85 -40 - Junction Temperature C QuickRAM Family Data Sheet Rev ...

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... CCIO CC MAX 400 us Time /V rails must take 400 µs or longer to reach the maximum value CC CCIO to the maximum voltage faster than 400 µs can cause the device to behave -V ) CCIO CC MAX V CC ≤ 500 mV when ramping up the power supply. © 2007 QuickLogic Corporation ...

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... TDI and TDO pins. For this test, the boundary scan register can be accessed via a data scan operation, allowing users to sample the functional data entering and leaving the device. © 2007 QuickLogic Corporation Figure 9: JTAG Block Diagram Instruction Decode ...

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... Can be configured as an input and/or output. Connect to 3.3 V supply. Connect to 5.0 V supply input tolerance is required, otherwise connect to 3.3 V supply. Connect to ground. Available on 456-PBGA only. Connect to ground plane on PCB if heat sinking desired. Otherwise may be left unconnected. Description not CC CC © 2007 QuickLogic Corporation ...

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... GND GCLK ACLK/I 34 © 2007 QuickLogic Corporation Figure 10: QL4009 – 68 Pin PLCC (Top View GND IO GCLK/I ACLK/I VCC GCLK/I GCLK/I QuickRAM IO QL4009-1PL68C Table 15: QL4009 – ...

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... VCC 67 GCLK/I 66 GCLK/I 65 ACLK/I 64 GCLK GND Function 84 PLCC Function I/O 64 ACLK/I I/O 65 GCLK/I I/O 66 GCLK/I VCCIO 67 VCC I/O 68 I/O I/O 69 I/O I/O 70 I/O I/O 71 I/O I/O 72 I/O TRSTB 73 I/O TMS 74 I/O I/O 75 TCK I/O 76 STM I/O 77 I/O I/O 78 I/O I/O 79 VCC I/O 80 I/O I/O 81 I/O GND 82 GND I/O 83 I/O GCLK/I 84 I/O © 2007 QuickLogic Corporation ...

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... VCC I/O © 2007 QuickLogic Corporation Figure 12: QL4009 – 100 Pin TQFP (Top View) QuickRAM QL4009-1PF100C Table 17: QL4009 – 100 TQFP Pinout Table Function 100TQFP TDI 51 I/O 52 I/O 53 I/O 54 I/O 55 I/O 56 I/O 57 I/O 58 I/O 59 GND 60 I/O 61 I/O 62 ...

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... VCC 67 GCLK ACLK GND Function 84 PLCC Function I/O 64 ACLK/I I I/O 66 GCLK/I VCCIO 67 VCC I/O 68 I/O I/O 69 I/O I/O 70 I/O I/O 71 I/O I/O 72 I/O TRSTB 73 I/O TMS 74 I/O I/O 75 TCK I/O 76 STM I/O 77 I/O I/O 78 I/O I/O 79 VCC I/O 80 I/O I/O 81 I/O GND 82 GND I I/O © 2007 QuickLogic Corporation ...

Page 17

... QL4016 – 100 TQFP/CQFP Pinout Diagram Figure 14: QL4016 – 100 Pin TQFP/CQFP (Top View) Pin 1 Pin 26 QL4016 – 144 TQFP Pinout Diagram Pin 1 Pin 37 © 2007 QuickLogic Corporation QuickRAM QL4016-1PF100C Figure 15: QL4016 – 144 Pin TQFP (Top View) QuickRAM QL4016-1PF144C QuickRAM Family Data Sheet Rev. M ...

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... I/O 133 NC NC I/O 134 94 69 I/O 135 NC NC I/O 136 I/O 137 NC NC GND 138 NC NC I/O 139 96 72 I/O 140 97 NC I/O 141 98 73 I/O 142 99 74 I/O 143 100 75 I/O 144 1 76 TCK 77 STM © 2007 QuickLogic Corporation Function I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O GND I/O I/O I/O VCCIO I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O TDO I/O ...

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... QL4036 – 144 TQFP Pinout Diagram Pin 1 Pin 37 QL4036 – 208 PQFP Pinout Diagram Pin 1 Pin 53 © 2007 QuickLogic Corporation Figure 16: QL4036 – 144 Pin TQFP (Top View) QuickRAM QL4036-1PF144C Figure 17: QL4036 – 208 Pin PQFP (Top View) QuickRAM QL4036-1PQ208C QuickRAM Family Data Sheet Rev. M ...

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... I/O 162 113 I/O 204 I/O 163 NC GND 205 I/O 164 NC I/O 206 I/O 165 114 VCC 207 I/O 166 115 I/O 208 I/O 167 116 I/O I/O 168 NC I/O © 2007 QuickLogic Corporation 144 Function TQFP 117 I/O 118 I/O 119 I/O 120 I/O NC I/O NC I/O 121 I/O NC I/O 122 GND 123 I/O 124 I/O NC I/O 125 I/O 126 GND 127 I/O 128 ...

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... QL4036 – 256 PBGA Pinout Diagram © 2007 QuickLogic Corporation Figure 18: QL4036 – 256 PBGA Pinout Diagram TOP View QuickRAM QL4036-1PB256C BOTTOM View QuickRAM Family Data Sheet Rev. M PIN A1 CORNER www.quicklogic.com • ...

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... Y4 I I/O V3 I/O Y6 I/O V4 I/O Y7 I I/O Y9 I/O V7 I/O Y10 NC V8 I/O Y11 I/O V9 I/O Y12 I/O V10 I/O Y13 VCC V11 I/O Y14 VCC V12 VCCIO Y15 I/O V13 I/O Y16 I/O V14 I/O Y17 I/O V15 I/O Y18 NC V16 I/O Y19 I/O V17 I/O Y20 I/O V18 I/O NC V19 TMS © 2007 QuickLogic Corporation Function I/O I/O I/O TDI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TRSTB I/O NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC ...

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... Pin 1 Pin 53 Pin 1 Pin 61 © 2007 QuickLogic Corporation Figure 19: QL4058 – 208 Pin PQFP (Top View) QuickRAM QL4058-1PQ208C Figure 20: QL4058 – 240 Pin PQFP (Top View) QuickRAM QL4058-1PQ240C QuickRAM Family Data Sheet Rev. M Pin 157 Pin 105 Pin 181 Pin 121 www.quicklogic.com • ...

Page 24

... VCC I/O 97 • • 24 www.quicklogic.com • • • • Table 22: QL4058 – 208/240 PQFP Pinout Table 208 240 208 Function Function PQFP PQFP PQFP 43 GND 98 84 I I/O 45 I/O 100 86 I/O 46 I/O 101 87 I/O 47 I/O 102 ...

Page 25

... QL4058 – 456 PBGA Pinout Diagram © 2007 QuickLogic Corporation Figure 21: QL4058 – 456 PBGA Pinout Diagram TOP View QuickRAM QL4058-1PB456C BOTTOM View QuickRAM Family Data Sheet Rev. M ...

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... D19 B20 I/O D20 B21 I/O D21 B22 I/O D22 B23 NC D23 B24 I/O D24 B25 I/O D25 B26 STM D26 • • 26 www.quicklogic.com • • • • Table 23: QL4058 – 456 PBGA Pinout Table Function 456 Function I/O E1 I/O I/O E2 I/O I/O E3 I/O TDO E4 I/O I/O E5 GND I/O E6 VCC I/O E7 GND I I/O E9 GND ...

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... Table 23: QL4058 – 456 PBGA Pinout Table (Continued) 456 Function 456 Function T1 I I/O W22 T3 I/O W23 T4 I/O W24 T5 VCC W25 T11 GND/THERM W26 T12 GND/THERM Y1 T13 GND/THERM Y2 T14 GND/THERM Y3 T15 GND/THERM Y4 T16 GND/THERM Y5 T22 GND Y22 T23 I/O Y23 T24 I/O Y24 T25 NC Y25 T26 ...

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... Pin 1 Pin 61 • • 28 www.quicklogic.com • • • • Figure 22: QL4090 – 208 Pin PQFP/CQFP (Top View) QuickRAM QL4090-1PQ208C Figure 23: QL4090 – 240 Pin PQFP (Top View) QuickRAM QL4090-1PQ240C Pin 157 Pin 105 Pin 181 Pin 121 © 2007 QuickLogic Corporation ...

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... VCC I © 2007 QuickLogic Corporation 240 208 240 Function Function PQFP PQFP PQFP GND 98 84 I/O 145 I I/O 146 I/O 100 86 I/O 147 I/O 101 87 I/O 148 I/O 102 88 I/O 149 I/O 103 89 I/O 150 ...

Page 30

... Figure 24: QL4090 – 456 PBGA Pinout Diagram TOP View QuickRAM QL4090-1PB456C BOTTOM View PIN A1 CORNER © 2007 QuickLogic Corporation ...

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... D17 B18 I/O D18 B19 I/O D19 B20 I/O D20 B21 I/O D21 B22 I/O D22 B23 I/O D23 B24 I/O D24 B25 I/O D25 B26 STM D26 © 2007 QuickLogic Corporation Table 25: QL4090 – 456 PBGA Pinout Table 456 Function 456 I/O E1 I/O H23 I/O E2 I/O H24 I/O E3 I/O H25 TDO E4 I/O H26 I/O E5 GND I/O E6 VCC I/O ...

Page 32

... AD24 I/O AF12 AD25 I/O AF13 AD26 I/O AF14 AE1 TDI AF15 AE2 I/O AF16 AE3 I/O AF17 AE4 I/O AF18 AE5 I/O AF19 AE6 I/O AF20 AE7 I/O AF21 AE8 I/O AF22 AE9 I/O AF23 AE10 I/O AF24 AE11 I/O AF25 AE12 I/O AF26 AE13 I/O AE14 I/O AE15 I/O AE16 I/O © 2007 QuickLogic Corporation Function I/O I/O I/O I/O I/O I/O NC TMS I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O ...

Page 33

... Package Mechanical Drawings 68 PLCC Mechanical Drawing © 2007 QuickLogic Corporation QuickRAM Family Data Sheet Rev. M www.quicklogic.com • • 33 • • • • ...

Page 34

... QuickRAM Family Data Sheet Rev PLCC Mechanical Drawing • • 34 www.quicklogic.com • • • • © 2007 QuickLogic Corporation ...

Page 35

... CQFP Mechanical Drawing © 2007 QuickLogic Corporation QuickRAM Family Data Sheet Rev. M www.quicklogic.com • • 35 • • • • ...

Page 36

... QuickRAM Family Data Sheet Rev. M 100 TQFP Mechanical Drawing • • 36 www.quicklogic.com • • • • © 2007 QuickLogic Corporation ...

Page 37

... TQFP Packaging Drawing © 2007 QuickLogic Corporation QuickRAM Family Data Sheet Rev. M www.quicklogic.com • • 37 • • • • ...

Page 38

... QuickRAM Family Data Sheet Rev. M 144 TQFP Packaging Drawing (Continued) • • 38 www.quicklogic.com • • • • © 2007 QuickLogic Corporation ...

Page 39

... CQFP Mechanical Drawing © 2007 QuickLogic Corporation QuickRAM Family Data Sheet Rev. M www.quicklogic.com • • 39 • • • • ...

Page 40

... QuickRAM Family Data Sheet Rev. M 208 PQFP Mechanical Drawing • • 40 www.quicklogic.com • • • • © 2007 QuickLogic Corporation ...

Page 41

... PQFP Mechanical Drawing © 2007 QuickLogic Corporation QuickRAM Family Data Sheet Rev. M www.quicklogic.com • • 41 • • • • ...

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... QuickRAM Family Data Sheet Rev. M 256 PBGA Mechanical Drawing • • 42 www.quicklogic.com • • • • © 2007 QuickLogic Corporation ...

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... PBGA Mechanical Drawing © 2007 QuickLogic Corporation QuickRAM Family Data Sheet Rev. M www.quicklogic.com • • 43 • • • • ...

Page 44

... PF100 (PFN100)* = 100-pin TQFP PF144 (PFN144)* = 144-pin TQFP PQ208 (PQN208)* = 208-pin PQFP PQ240 = 240-pin PQFP PB256 (PBN256)* = 256-ball PBGA PB456 (PBN456)*= 456-ball PBGA CF100 = 100-pin CQFP CF208 = 208-pin CQFP Table 26. Device QL4036 QL4058 Pitch Pin Pitch 0.5 mm 208 PQFP 0.5 mm 0.5 mm 240 PQFP 0.5 mm 1.27 mm 456 PBGA 1 ...

Page 45

... Copyright and Trademark Information Copyright © 2007 QuickLogic Corporation. All Rights Reserved. The information contained in this document is protected by copyright. All rights are reserved by QuickLogic Corporation. QuickLogic Corporation reserves the right to modify this document without any obligation to notify any person or entity of such revision. Copying, duplicating, selling, or otherwise distributing any part of this product without the prior written consent of an authorized representative of QuickLogic is prohibited ...

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