lc8904q Sanyo Semiconductor Corporation, lc8904q Datasheet - Page 16

• Manufacturer Part Number: lc8904q
• Description: Digital Audio Interface Receiver
• Manufacturer: Sanyo Semiconductor Corporation

The CLK, CLKMD, CLKOUT1, and CLKOUT2 Pins
The output clocks for the CLKOUT1 and CLKOUT2 clock output pins is selected by the CLK and CLKMD pins.
Note: 1. The crystal oscillator clock is output in analog source mode.
The SUB1 and SUB2 Pins
These pins indicate the sampling frequency of the input data.
The state “#1” is indicated on a PLL lock error and in analog source mode.
Also note that the DATAOUT and EMPHA pins will output low levels in this state.
The EMPHA Pin
The ERROR pin and Error Processing
ERROR pin: When an error exists in the input data or when the PLL circuit is in the unlocked state, this pin goes high
and holds that high level for about 200 to 300 ms after data demodulation returns to normal. The table below lists the
data processing applied when an error occurs.
Note: * The CRC flags go low when a PLL lock error occurs.
Note: PLL lock error determination is performed starting from preamble detection.
The XMODE Pin
This pin is used for system reset. The system will start to operate normally if this pin is set high after the power supply
has risen to at least 4.5 V. If XMODE is set low, the VCO free-running clock will be output from the CLKOUT1 pin.
After application of power, the system will be reset if the XMODE pin is set low again.
Up to eight consecutive parity errors
Eight or more consecutive parity errors
PLL lock error
EMPHA
SUB1
SUB2
CLK
2. The 256fs clock has a H:L duty ratio of 2:1 when the CLK pin is low.
Pin
Pin
H
L
Outputs a 384fs clock
Outputs a 512fs clock
Type of error
32 kHz
H
H
Emphasis applied
CLKOUT
H
*1
44.1 kHz
L
L
48 kHz
Previous data
Emphasis not applied
DATAOUT
H
L
L
L
CLKMD
LC8904Q
H
L
L
#1
H
L
Outputs a 256fs clock
Outputs a 128fs clock
SUB1, SUB2
Output
Output
#1
CLKOUT2
Analog source mode
*2
L
Output
Output
C bit
L
Sub Q*
No. 5014-16/20
Output
Output
L