k4x56163pe-lg Samsung Semiconductor, Inc., k4x56163pe-lg Datasheet - Page 8

• Manufacturer Part Number: k4x56163pe-lg
• Description: 16m X16 Mobile Ddr Sdram
• Manufacturer: Samsung Semiconductor, Inc.

K4X56163PE-L(F)G
the EMRS command needs to be issued only when either PASR or DS is used. The default state without EMRS command issued is
+85 C, all 4 banks refreshed and the half size of driver strength. The extended mode register is written by asserting low on CS, RAS,
CAS, WE and high on BA1 ,low on BA0(The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into
the extended mode register). The state of address pins A0 ~ A11 in the same cycle as CS, RAS, CAS and WE going low is written in
the extended mode register. Two clock cycles are required to complete the write operation in the extended mode register. Even if the
power-up sequence is finished and some read or write operations is executed afterward, the mode register contents can be changed
with the same command and four clock cycles. But this command must be issued only when all banks are in the idle state. A0 - A2
are used for partial array self refresh and A5 - A6 are used for driver strength. "High" on BA1 and"Low" on BA0 are used for EMRS.
All the other address pins except A0,A1,A2, BA1, BA0 must be set to low for proper EMRS operation. Refer to the table for specific
codes.
Extended MRS for PASR(Partial Array Self Refresh) &
TCSR(Internal Temperature Compensated Self Refresh)
Extended Mode Register Set(EMRS)
The extended mode register is designed to support partial array self refresh or driver strength. EMRS cycle is not mandatory and
BA1
1
BA0
A
0
0
0
1
1
6
A
0
1
0
1
A12
5
0
Driver Strength
DS
A11
0
Full
1/2
1/4
1/8
A10
0
A9
0
A8
0
Self refresh cycle is controlled
automatically by internal tem-
perature sensor and control cir-
cuit according to the two
temperature ; Max 40 C,Max
85 C
A7
0
Internal TCSR
8
A6
DS
A5
A4
0
A3
0
Mobile-DDR SDRAM
A
0
0
0
0
1
1
1
1
2
A2
A
0
0
1
1
0
0
1
1
1
PASR
A
A1
0
1
0
1
0
1
0
1
0
PASR
A0
# of Banks
Full Array
Reserved
Reserved
Reserved
Reserved
Reserved
1/2 Array
1/4 Array
March 2004
Address Bus
Mode Register