IDT49FCT805A IDT [Integrated Device Technology], IDT49FCT805A Datasheet - Page 6

• Manufacturer Part Number: IDT49FCT805A
• Description: FAST CMOS BUFFER/CLOCK DRIVER
• Manufacturer: IDT [Integrated Device Technology]

IDT49FCT805/806/A
FAST CMOS BUFFER/CLOCK DRIVER
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
PULSE SKEW - t
ENABLE AND DISABLE TIMES
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control
2. Pulse Generator for All Pulses: f
PACKAGE DELAY
Generator
OUTPUT
Disable-HIGH
Pulse
INPUT
OUTPUT
NORMALLY
NORMALLY
INPUT
CONTROL
OUTPUT
OUTPUT
INPUT
HIGH
LOW
V
IN
SWITCH
CLOSED
R
SWITCH
OPEN
ENABLE
T
SK
t
t
D.U.T.
t
PZL
PZH
t
PLH
PLH
V
(p)
CC
t
SK(p)
t
R
= |t
1.5V
1.5V
3.5V
1.0MHz; t
0V
V
OUT
PHL -
t
t
C
PLH
PHZ
50pF
F
t
DISABLE
t
L
PHL
PHL
|
2.5ns; t
t
t
PLZ
F
500
500
0.3V
0.3V
R
0.8V
2.0V
2.5ns
V
3V
1.5V
0V
1.5V
V
OH
2574 drw 07
2574 drw 08
OL
2574 drw 10
2574 drw 12
3V
1.5V
0V
3.5V
V
V
0V
7.0V
3V
1.5V
0V
1.5V
V
V
OL
OH
OL
OH
9.1
PACKAGE 1 OUTPUT
PACKAGE 2 OUTPUT
ENABLE AND DISABLE TIME
SWITCH POSITION
DEFINITIONS:
C
R
PACKAGE SKEW - t
Package 1 and Package 2 are same device type and speed grade
OUTPUT SKEW - t
L
T
= Load capacitance: includes jig and probe capacitance.
= Termination resistance: should be equal to Z
Generator.
OUTPUT 1
OUTPUT 2
Disable HIGH
Disable LOW
Enable HIGH
INPUT
Enable LOW
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Test
INPUT
t
SK(o)
SK
t
PLH1
t
SK
= |t
SK(t)
t
(o)
PLH2
t
PLH1
t
PLH2 -
SK(o)
(t)
t
= |t
PLH2
t
SK(t)
PLH2 -
t
PLH1
t
t
|
PLH1
PHL1
t
or
t
PHL2
PHL1
t
SK(o)
|t
OUT
t
PHL2 -
PHL2
|
Switch
Closed
Open
or
t
SK(t)
of the Pulse
|t
PHL2 -
t
PHL1
V
3V
1.5V
0V
V
1.5V
V
V
1.5V
t
|
PHL1
OL
OL
OH
OH
2574 drw 09
2574 drw 11
2574 lnk 11
V
V
V
3V
1.5V
0V
1.5V
1.5V
V
OH
OL
OH
OL
|
6