IDT72261 IDT [Integrated Device Technology], IDT72261 Datasheet - Page 2

• Manufacturer Part Number: IDT72261
• Description: CMOS SUPERSYNC FIFOO 16,384 x 9, 32,768 x 9
• Manufacturer: IDT [Integrated Device Technology]

IDT72261/72271 SyncFIFO
16,384 x 9, 32,768 x 9
state of the FWFT/SI pin during Master Reset determines the
mode in use.
OR
Ready), and
selected in the IDT Standard Mode.
Through Mode.
receive data.
available for reading.
memory. This flag can always be used irrespective of mode.
in memory. They, also, can be used irrespective of mode.
Programmable offsets determine the flag threshold and can
be loaded by two methods: parallel or serial. Two default
offset settings are also provided, such that
127 or 1023 locations from the empty boundary and the
threshold can be set at 127 or 1023 locations from the full
NOTES
1. DNC = Do not connect.
2. This pin may either be tied to ground or left open.
PIN CONFIGURATIONS
The
HF
PAE
The IDT72261/72271 FIFOs have five flag functions,
(Empty Flag or Output Ready),
is a flag whose threshold is fixed at the half-way point in
:
,
IR
PAF
and
HF
can be programmed independantly to any point
OR
OR
(Half-full Flag). The
IR
functions are selected in the First Word Fall
indicates that data contained in the FIFO is
PIN 1
indicates that the FIFO has free space to
GND
GND
GND
GND
GND
GND
GND
GND
GND
V
V
WEN
SEN
D8
D7
FS
CC
CC
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
FF
EF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
/
IR
and
(Full Flag or Input
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PAE
FF
STQFP (PP64-1, order code: TF)
functions are
can be set at
TQFP (PN64-1, order code: PF)
PAF
EF
TOP VIEW
/
boundary. All these choices are made with
Reset
the offset registers via the Serial Input (SI). In the parallel
method,
registers via D
offsets in parallel from Q
parallel offset loading is selected.
set to the first location of the FIFO. The FWFT line selects IDT
Standard Mode or FWFT Mode. The
partial flag default settings (127 or 1023) and, also, serial or
parallel programming. The flags are updated accordingly.
pointers to the first location of the memory. However, the
mode setting, programming method, and partial flag offsets
are not altered. The flags are updated accordingly.
useful for resetting a device in mid-operation, when repro-
gramming offset registers may not be convenient.
In the serial method,
During Master Reset (
The Partial Reset (
.
WEN
MILITARY AND COMMERCIAL TEMPERATURE RANGES
n
together with
.
REN
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
together with
SEN
PRS
MRS
n
LD
) also sets the read and write
together with
regardless of whether serial or
), the read and write pointers are
3036 drw 02
can be used to load the offset
DNC
DNC
GND
DNC
DNC
V
DNC
DNC
DNC
GND
DNC
DNC
Q8
Q7
Q6
GND
LD
CC
LD
can be used to read the
pin selects one of two
LD
LD
are used to load
during Master
PRS
2
is