SST49LF004B-33-4C-EI SST [Silicon Storage Technology, Inc], SST49LF004B-33-4C-EI Datasheet
SST49LF004B-33-4C-EI
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SST49LF004B-33-4C-EI Summary of contents
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... Byte-Program Time: 14 µs (typical) – Chip Rewrite Time: 8 seconds (typical) PRODUCT DESCRIPTION The SST49LF004B flash memory device is designed to interface with host controllers (chipsets) that support a low- pin-count (LPC) interface for BIOS applications. The SST49LF004B device complies with Intel’s LPC Interface Specification 1 ...
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... Silicon Storage Technology, Inc. 4 Mbit LPC Firmware Flash or hardware does not have to be calibrated or correlated to the cumulative number of Erase cycles as is necessary with alternative flash memory technologies, whose Erase and Program times increase with accumulated Erase/Pro- gram cycles. 2 SST49LF004B S71232-02-000 12/03 ...
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... Mbit LPC Firmware Flash SST49LF004B LPC MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Firmware Memory Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Firmware Memory Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 LPC Memory Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 LPC Memory Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Abort Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Response to Invalid Fields for Firmware Memory Cycle Response to Invalid Fields for LPC Memory Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Multiple Device Selection ...
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... FIGURE 19: Block-Erase Timing Diagram (PP Mode FIGURE 20: Chip-Erase Timing Diagram (PP Mode FIGURE 21: Software ID Entry and Read (PP Mode FIGURE 22: Software ID Exit (PP Mode FIGURE 23: AC Input/Output Reference Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 FIGURE 24: A Test Load Example ©2003 Silicon Storage Technology, Inc. 4 Mbit LPC Firmware Flash 4 SST49LF004B S71232-02-000 12/03 ...
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... Mbit LPC Firmware Flash SST49LF004B LIST OF TABLES TABLE 1: Pin Description TABLE 2: Product Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 TABLE 3: Firmware and LPC Memory Cycles START Field Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 TABLE 4: Firmware Memory Read Cycle Field Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 TABLE 5: Firmware Memory Write Cycle TABLE 6: LPC Memory Read Cycle Field Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 TABLE 7: LPC Memory Write Cycle Field Definitions ...
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... INIT# LAD[3:0] LCLK FWH/LPC LFRAME# Interface ID[3:0] GPI[4:0] R/C# A[10:0] Programmer DQ[7:0] Interface OE# WE# ©2003 Silicon Storage Technology, Inc. X-Decoder Address Buffers & Latches Control Logic MODE RST Mbit LPC Firmware Flash SST49LF004B SuperFlash Memory Y-Decoder I/O Buffers and Data Latches 1232 ILL B1.0 S71232-02-000 12/03 ...
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... Mbit LPC Firmware Flash SST49LF004B PIN ASSIGNMENTS A7(GPI1) A6 (GPI0) A5 (WP#) A4 (TBL#) A3 (ID3) A2 (ID2) A1 (ID1) A0 (ID0) DQ0 (LAD0 Designates LPC Mode FIGURE SSIGNMENTS FOR NC (NC) MODE (MODE) NC (NC) NC (NC) NC (NC) NC (NC) A10 (GPI4) NC (NC) R/C# (LCLK (NC) RST# (RST#) NC (NC) ...
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... The outputs are in tri-state when OE# is high gate the data output buffers control the Write operations. X These pins must be left unconnected provide power supply (3.0-3.6V Circuit ground (0V reference) N/A N/A Unconnected pins Mbit LPC Firmware Flash SST49LF004B ) for PP mode and low ( T1.0 1232 S71232-02-000 12/03 ) ...
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... The Top Boot Lock (TBL#) and Write Protect (WP#) pins are provided for hardware write protection of device mem- ory in the SST49LF004B. The TBL# pin is used to write pro- tect 64 KByte at the highest memory address range for the SST49LF004B. WP# pin write protects the remaining sec- tors in the flash memory ...
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... Address shown in this column is for boot device only. Address locations should appear elsewhere in the 4 GByte system memory map depending on ID strapping values on ID[3:0] pins when multiple LPC memory devices are used in a system. 2. The device ID for SST49LF004B is the same as SST49LF004A Mbit LPC Firmware Flash SST49LF004B ...
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... The SST49LF004B flash memory device operates in two distinct interface modes: the LPC mode and the Parallel Programming (PP) mode. In LPC mode, communication between the Host and the SST49LF004B occurs via the 4- bit I/O communication signals, LAD[3:0], and LFRAME mode, the device is controlled via the 11 addresses, ...
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... ZZZZ is the least-significant nibble of the data byte. OUT ZZZZ is the most-significant nibble of the data byte. OUT then In this clock cycle, the SST49LF004B drives the bus to all Float ones and then floats the bus prior to the next clock cycle. This is the first part of the bus “turnaround cycle.” ...
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... OUT then Float In this clock cycle, the SST49LF004B drives the bus to all '1's and then floats the bus prior to the next clock cycle. This is the first part of the bus “turnaround cycle.” ...
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... In this clock cycle, the host drives the bus to all 1s and then then Float floats the bus. This is the first part of the bus “turnaround cycle.” Float The SST49LF004B takes control of the bus during this cycle. then OUT OUT The SST49LF004B outputs the value 0000b indicating that it has received data ...
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... The SST49LF004B outputs the values 0000, indicating that it has received data or a flash command. 1111 OUT then Float In this clock cycle, the SST49LF004B drives the bus to all '1's and then floats the bus. This is the first part of the bus “turnaround cycle.” Float then IN Host resumes control of the bus during this cycle ...
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... ID mismatch: ID information is included in the address bits of every LPC Memory cycle. Address bits A used to select the device with proper IDs. The SST49LF004B will compare the ID bits in the address field with ID[3:0]. If the ID bits in the address do not correspond to the hardware ID pins the device will ignore the cycle. See Multiple Device Selection section for details ...
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... For Firmware Memory Read/Write cycles, hardware strap- ping values on ID[3:0] must match the values in IDSEL field. See Table 8 for multiple device selection configura- tions. The SST49LF004B will compare the IDSEL field with ID[3:0]'s strapping values. If there is a mismatch, the device will ignore the reminder of the cycle. ...
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... Write cycle, otherwise the rejection is valid. Data# Polling When the SST49LF004B device is in the internal Program operation, any attempt to read D[7] will produce the com- plement of the true data. Once the Program operation is completed, D[7] will produce true data. Note that even ...
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... Mbit LPC Firmware Flash SST49LF004B TABLE 10 LOCK OCKING EGISTERS Register T_BLOCK_LK T_MINUS01_LK T_MINUS02_LK T_MINUS03_LK T_MINUS04_LK T_MINUS05_LK T_MINUS06_LK T_MINUS07_LK TABLE 11 LOCK OCKING EGISTER Reserved Bit [7..2] Lock-Down Bit [1] 000000 000000 000000 000000 JEDEC ID Registers The JEDEC ID registers provide access to the manufac- turer and device ID information with a single Read cycle ...
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... R/C# and the column address is latched on the rising edge of R/C#. Read The Read operation of the SST49LF004B device is con- trolled by OE#. OE# is the output control and is used to gate data from the output pins. Refer to the Read cycle tim- ing diagram, Figure 13, for further details. ...
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... X can but no other value Data# Polling ( When the SST49LF004B device is in the internal Program operation, any attempt to read DQ will produce the com- 7 plement of the true data. Once the Program operation is completed, DQ will produce true data. Note that even 7 ...
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... SA for Sector-Erase Address for Block-Erase Address X 6. Chip-Erase is supported in PP mode only 7. SST Manufacturer’ BFH, is read with A SST49LF004B Device ID = 60H, is read with A 8. Both Software ID Exit operations are equivalent ©2003 Silicon Storage Technology, Inc. S EQUENCE 1 1 2nd 3rd ...
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... Mbit LPC Firmware Flash SST49LF004B ELECTRICAL SPECIFICATIONS The AC and DC specifications for the LPC interface signals (LA0[3:0], LFRAME, LCLCK and RST#) are defined in Sec- tion 4.2.2.4 of the PCI local bus specification, Rev. 2.1. Refer to Table 14 for the DC voltage and current specifications. Refer to Tables 18 through 24 for the AC timing specifications for Clock, Read, Write, and Reset operations. ...
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... min, LFRAME OWER UP IMINGS Minimum =3.3V, Ta=25 °C, f=1 Mhz, other pins open) Test Condition Mbit LPC Firmware Flash SST49LF004B and Address Input =V (PP mode LPC mode PP mode TRC min Max DD DD and Address Input =V (PP mode) ...
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... Mbit LPC Firmware Flash SST49LF004B TABLE 17 ELIABILITY HARACTERISTICS Symbol Parameter 1 N Endurance END 1 T Data Retention Latch Up LTH 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 18 LOCK ...
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... V DD -17.1 OUT Equation C - Equation D DD 26.7 V OUT -25+(V +1)/0.015 IN 25+(V -V -1)/0.015 Mbit LPC Firmware Flash SST49LF004B ) ODE Min Max Units Conditions mA 0 < V 0.3V OUT DD mA 0.3V < V < 0.9V DD OUT 1 0.7V < V < ...
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... Mbit LPC Firmware Flash SST49LF004B (Valid Output Data) (Float Output Data) FIGURE UTPUT IMING ARAMETERS LCLK LAD [3:0] (Valid Input Data) FIGURE 10 NPUT IMING ARAMETERS ©2003 Silicon Storage Technology, Inc. V LCLK TEST T VAL LAD [3:0] LAD [3: OFF (LPC M ...
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... Timing parameters must be met with no more over =3.0-3.6V (LPC M ) ODE reset procedure is performed during a Program or Erase operation, T PRST T KRST T T RSTF (LPC M ) ODE 28 4 Mbit LPC Firmware Flash SST49LF004B ) ODE Units V/ns Min Max Units 1 100 100 RSTP Sector-/Block-Erase T RSTE ...
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... Mbit LPC Firmware Flash SST49LF004B TABLE 23 ESET IMING ARAMETERS Symbol Parameter T V stable to Reset Low PRST DD T RST# Pulse Width RSTP T RST# Low to Output Float RSTF 1 T RST# High to Row Address Setup RST T RST# Low to reset during Sector-/Block-Erase or Program ...
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... ODE DD Min 270 =3.0-3.6V (PP M IMING ARAMETERS DD Min 100 100 Mbit LPC Firmware Flash SST49LF004B ) Max Units ns µ 120 T24.0 1232 ) ODE Max Units µ ...
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... Mbit LPC Firmware Flash SST49LF004B RST# Addresses R/ WE# OE# High-Z DQ 7-0 FIGURE 13 EAD YCLE IMING T RST RST# Row Address Addresses T AS R/C# OE# WE# DQ 7-0 FIGURE 14 RITE YCLE IMING ©2003 Silicon Storage Technology, Inc. T RST T RC Row Address Column Address T AS ...
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... ATA OLLING IMING Row Column Addresses R/C# WE# OE FIGURE 16 OGGLE IT IMING ©2003 Silicon Storage Technology, Inc. Column T OEP IAGRAM ODE T OET D ( IAGRAM ODE 32 4 Mbit LPC Firmware Flash SST49LF004B D# D 1232 F15.0 D 1232 F15.0 S71232-02-000 12/03 ...
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... Mbit LPC Firmware Flash SST49LF004B A 14-0 (Internal A ) 5555 MS-0 R/C# OE# WE Byte-Program Address A = Most Significant Address MS FIGURE 17 YTE ROGRAM IMING A 14-0 (Internal A ) 5555 MS-0 R/C# OE Sector Address X FIGURE 18 ECTOR RASE IMING ©2003 Silicon Storage Technology, Inc. 2AAA 5555 (PP M ...
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... Silicon Storage Technology, Inc. 2AAA 5555 5555 ( IAGRAM ODE 2AAA 5555 5555 ( IAGRAM ODE 34 4 Mbit LPC Firmware Flash SST49LF004B 2AAA BA X Internal Erase Starts 1232 F18.0 2AAA 5555 Internal Erase Starts 1232 F19.0 S71232-02-000 12/03 ...
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... Mbit LPC Firmware Flash SST49LF004B A 14-0 (Internal A ) 5555 MS-0 R/ 7-0 FIGURE 21 OFTWARE NTRY AND A 14-0 (Internal A ) MS-0 R/C# OE# WE# DQ 7-0 FIGURE 22 OFTWARE XIT ©2003 Silicon Storage Technology, Inc. 2AAA 5555 T WPH ( EAD ODE 5555 2AAA 5555 ...
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... V (0.5 ). Input rise and fall times (10 EFERENCE AVEFORMS TO TESTER 1232 F23 Mbit LPC Firmware Flash SST49LF004B V OT OUTPUT 1232 F22.0 ) for a logic “0”. Measurement reference 90%) are <5 ns. Note Test IT INPUT Test OT OUTPUT HIGH Test ...
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... XX Valid combinations for SST49LF004B SST49LF004B-33-4C-EI SST49LF004B-33-4C-NH SST49LF004B-33-4C-EIE SST49LF004B-33-4C-NHE Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. ©2003 Silicon Storage Technology, Inc. ...
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... SIDE VIEW .112 .106 .029 .020 R. .040 x 30˚ R. .023 .030 MAX. .021 .013 .400 .032 BSC .026 .050 BSC .015 Min. .095 .075 .140 .125 (PLCC Mbit LPC Firmware Flash SST49LF004B BOTTOM VIEW .530 .490 .032 .026 32-plcc-NH-3 S71232-02-000 12/03 ...
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... Mbit LPC Firmware Flash SST49LF004B Pin # 1 Identifier 0.70 0.50 20.20 19.80 Note: 1. Complies with JEDEC publication 95 MO-142 CD dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (max/min). 3. Coplanarity: 0 Maximum allowable mold flash is 0. the package ends, and 0.25 mm between leads. 40 ...