m5m44260cj Mitsumi Electronics, Corp., m5m44260cj Datasheet - Page 29

• Manufacturer Part Number: m5m44260cj
• Description: Fast Page Mode 4194304-bit 262144-word 16-bit Dynamic
• Manufacturer: Mitsumi Electronics, Corp.

29
M5M44260CJ,TP-5,-5S : Under development
2. Burst refresh during Read/Write operation
(A) Timing diagram
RAS
Table 3
RAS
Definition of CBR burst refresh
Definition of RAS only burst refresh
(B) Definition of burst refresh
2.1 CBR burst refresh
Read / Write Cycle
CBR burst
refresh
RAS only
burst refresh
Switching from read/write operation to self refresh operation.
The time interval t
the first CBR refresh cycle during read/write operation period
to the falling edge of RAS signal at the start of self refresh
operation should be set within 8.2 ms.
Switching from self refresh operation to read/write operation.
The time interval t
the end of self refresh operation to the falling edge of RAS
signal in the last CBR refresh cycle during read/write operation
period should be set within 8.2 ms.
The CBR burst refresh performs more than 512 continuous
CBR cycles within 8.2 ms.
All combination of nine row address signals (A
selected during 512 continuous RAS only refresh cycles
within 8.2 ms.
NSB
SNB
Read / Write
refresh cycles
refresh cycles
Read / Write
512 cycles
t
from the falling edge of RAS signal in
from the rising edge of RAS signal at
NSB
Self Refresh
first
8.2ms
t
NSB
t
NSB
refresh cycles
+t
FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
511 cycles
SNB
8.2ms
Self Refresh
t
SNB
Read / Write
8.2ms
8.2ms
0
~A
Self Refresh
t
RASS
8
) are
100µs
M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S
read/write cycles
2.2 RAS only burst refresh
Switching from read/write operation to self refresh operation.
The time interval from the falling edge of RAS signal in the
first RAS only refresh cycle during read/write operation period
to the falling edge of RAS signal at the start of self refresh
operation should be set within t
Switching from self refresh operation to read/write operation.
The time interval from the rising edge of RAS signal at the end
of self refresh operation to the falling edge of RAS signal in
the last RAS only refresh cycle during read/write operation
period should be set within t
refresh cycles
511 cycles
t
SNB
Read / Write
refresh Cycles
last
SNB
NSB
(shown in table 3).
(shown in table 3).
MITSUBISHI LSIs