mh89760b Mitel, mh89760b Datasheet - Page 22

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mh89760b

Manufacturer Part Number
mh89760b
Description
St-bus? Family T1/esf Framer & Interface
Manufacturer
Mitel
Datasheet

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MH89760B
The switch matrix can be built so that the maximum
throughput delay is 1 frame +2 channels. The switch
matrix will not only route data channels to their
destination, but it will also route the received
signalling bits through to the destination channel.
This is necessary because the receiving MH89760B
decodes the T1 stream, and the transmitting
MH89760B has to reconstruct the outgoing T1
stream. In other words, there is no multiframe
integrity between received data and transmitted
data. The total throughput delay is one frame plus
ten ST-BUS channels for the MH89760B receiver,
2.5 ST-BUS channels for the MH89760B transmitter,
and one frame plus two ST-BUS channels for the
switch matrix for a total of 2.5 frames worst case.
The control block only interfaces with the switch
matrix. Besides routing channels and signalling
4-76
M
I
C
R
O
C1.5i
F0i
C4i
C2i
Switch
Matrix
Control
Matrix
AA AA
AAAA AAAA
AAAA
F0b
CVb
F0i
C4b
C20
AAAA AAAA
DPLL #2
MT8941
DPLL #1
AAAA AAAA
Figure 15 - Digital Access Cross Connect System (DACS)
F0i
C4i
AAAA AAAA
F0i
C4i
C8Kb
C12i
C16i
MT8980
AAAA
MT8980
A A
Clock
Generator
STo0
STo7
STo7
STo1
STo2
STo0
STi0
STi7
STi7
MHz Osc.
STi0
MHz Osc.
16.384
12.352
through to the proper destination, the switch matrix
must also supply the Master Control Words, and
monitor
MH89760B.
The clock generation block supplies the ST-BUS
clocks and the
synchronized to one of the T1 trunks. All of the
extracted 8 kHz outputs are NANDed together before
they are input to PLL #2 of the MT8941.
Phase-locked Loop #2 of the MT8941, will generate
ST-BUS clock signals for the MH89760Bs and the
MT8980s that are synchronized with the chosen T1
line. The E8Ko of all of the other MH89760Bs can be
tristated from the Master Control Word, which allows
the system controller to select any one of 128 T1
lines to act as the synchronization source. By
the
Master
DSTi
DSTo
C2i
F0i
C1.5i
DSTi
DSTo
C2i
F0i
C1.5i
T1 transmit
CSTi0
CSTo
CSTi1
CSTi0
CSTo
CSTi1
T1 Interfaces
Preliminary Information
MH89760B
MH89760B
Status
OUTA
OUTB
OUTA
OUTB
E8Ko
E8Ko
RxT
RxR
RxT
RxR
Words
clocks that
for
Equal-
Equal-
izer
izer
each
are

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