ST16C654 EXAR [Exar Corporation], ST16C654 Datasheet
ST16C654
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ST16C654 Summary of contents
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... The 100 pin package provides additional FIFO status outputs (TXRDY# and RXRDY# A-D), separate infrared transmit data outputs (IRTX A-D) and channel C external clock input (CHCCLK). The ST16C654/654D is compatible with the industry standard ST16C454 and ST16C654/554D OTE 1 Covered by U.S. Patent #5,649,122 ...
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... & & & & & ST16C654/654D REV. 5.0 ODE < & & ' & ...
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... PERATING D EVICE P N EMPERATURE ART UMBER S TATUS R ANGE Active ST16C654DCQ64 Active ST16C654DIQ64 Active ST16C654CQ100 Active ST16C654IQ100 TQFP P ODE AND ACKAGES ' & & & & ...
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... When 16/68# pin is at logic 0, this input becomes address line A4 which is used for channel selection in the Motorola bus interface When 16/68# pin is at logic 1, this input is chip select D (active low) to enable channel D in the device. When 16/68# pin is at logic 0, this input is not used and should be connected VCC. 4 ST16C654/654D REV. 5.0.0 D ESCRIPTION ...
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... To cover this limitation, two 64 pin TQFP packages ver- sions are offered. This pin is bonded to VCC internally in the ST16C654D so the INT outputs operate in the continuous interrupt mode. This pin is bonded to GND internally in the ST16C654 and therefore requires setting MCR bit-3 for enabling the interrupt output pins. ...
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... I UART channel A-D Receive Data or infrared receive data. Normal receive data input must idle at logic 1 condition UART channels A-D Carrier-Detect (active low) or general purpose input ST16C654/654D REV. 5.0.0 D ESCRIPTION ...
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... ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO REV. 5.0.0 Pin Description 64-TQFP 100-QFP 68-PLCC N AME RIA RIB RIC RID ANCILLARY SIGNALS XTAL1 25 35 XTAL2 26 36 16/68 CLKSEL 21 30 CHCCLK - - RESET 27 37 (RESET#) VCC 4, 35, 52 13, 47, 10, 61, ...
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... In the 16 mode INTSEL and MCR bit-3 can be configured to provide a software controlled or continuous interrupt capability. Due to pin limitations for the 64 pin 654 this feature is offered by two different TQFP packages. The ST16C654DCV operates in the continuous interrupt enable mode by internally bonding INTSEL to VCC. The ST16C654CV operates in conjunction with MCR bit-3 by internally bonding INTSEL to GND ...
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... UART. No clock (oscillator nor external clock) is required to operate a data bus transaction. Each bus cycle is asynchronous using CS# A-D, IOR# and IOW# or CS#, R/W#, A4 and A3 inputs. All four UART channels share the same data bus for host operations. A typical data bus interconnection for Intel and Motorola mode is shown ST16C654/654D T IGURE YPICAL ' ' ...
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... Channel A selected Channel B selected Channel C selected Channel D selected Channels A-D selected See Table A HANNEL ELECT UNCTION N/A N/A UART de-selected 0 0 Channel A selected 0 1 Channel B selected 1 0 Channel C selected 1 1 Channel D selected 10 ST16C654/654D REV. 5.0.0 ODE ODE ...
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... ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO REV. 5.0.0 2.4 Channels A-D Internal Registers Each UART channel in the 654 has a set of enhanced registers for control, monitoring and data loading and unloading. The configuration register set is compatible to those already available in the standard single 16C550. These registers function as data holding registers (THR/RHR), interrupt status and control registers ...
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... FIFO is full 300 . - - -1) to obtain a 16X sampling rate clock of the serial data rate. The 12 ST16C654/654D REV. 5.0.0 C A-D ODE FOR HANNELS ) NABLED FCR Bit (DMA Mode Enabled) “Section ...
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... ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO REV. 5.0 IGURE AUD ATE ffe r Table 6 shows the standard data rates available with a 14.7456 MHz crystal or external clock at 16X sampling rate. When using a non-standard frequency crystal or external clock, the divisor value can be calculated for DLL/DLM with the following equation ...
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... FIFO AND LOW ONTROL ODE RX FIFO THR Interrupt (ISR bit-1) falls below the program m ed Trigger Level and then when becomes em pty. FIFO is Enabled by FCR bit-0=1 Transm it Data S hift Register (TSR) 14 ST16C654/654D REV. 5.0 NOF IFO1 ...
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... ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO REV. 5.0.0 2.10 Receiver The receiver section contains an 8-bit Receive Shift Register (RSR) and 64 bytes of FIFO which includes a byte-wide Receive Holding Register (RHR). The RSR uses the 16X clock for timing. It verifies and validates every bit on the incoming character in the middle of each data bit. On the falling edge of a start or false start bit, an internal receiver counter starts counting at the 16X clock rate ...
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... Trigger=16 desired FIFO trigger level. FIFO is Enabled by FCR bit-0=1 Data fills to RTS# de-asserts when data fills above the flow 56 control trigger level to suspend remote transmitter. Enable by EFR bit-6=1, MCR bit-1. Receive Data Figure 11): 16 ST16C654/654D REV. 5.0.0 M ODE Receive Data Characters ...
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... ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO REV. 5.0.0 F 11. A RTS CTS F IGURE UTO AND Local UART UARTA Receiver FIFO Trigger Reached Auto RTS Trigger Level Transmitter Auto CTS Monitor Assert RTS# to Begin Transmission 1 RTSA# 2 CTSB# TXB Data Starts RXA FIFO Receive ...
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... TO 5.5V QUAD UART WITH 64-BYTE FIFO (See Table 15), the 654 compares one or two sequential receive data UTO ON OFF OFTWARE LOW OFF HARACTER S ENT ( ) CHARACTERS IN RX FIFO 18 ST16C654/654D REV. 5.0.0 ONTROL HARACTER S ENT ( ) CHARACTERS IN RX FIFO ...
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... ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO REV. 5.0.0 2.15 Infrared Mode The 654 UART includes the infrared encoder and decoder compatible to the IrDA (Infrared Data Association) version 1.0. The IrDA 1.0 standard that stipulates the infrared encoder sends out a 3/ bit wide HIGH- pulse for each “0” bit in the transmit data stream. This signal encoding reduces the on-time of the infrared LED, hence reduces the power consumption. See The infrared encoder and decoder are enabled by setting MCR register bit ‘ ...
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... CTS#, DSR# CD# and RI# inputs are ignored. Caution: the RX input must be held to a logic 1 during loopback test else upon exiting the loopback test the UART may detect and report a false “break” signal. 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO 37. If the input lines are floating or are toggling while the 654 is in sleep 20 ST16C654/654D REV. 5.0.0 ...
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... ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO REV. 5.0 IGURE NTERNAL OOP Transmit Shift Register Receive Shift Register ACK IN HANNEL AND VCC (THR/FIFO) MCR bit-4=1 (RHR/FIFO) VCC RTS# CTS# VCC DTR# DSR# OP1# RI# OP2# CD ...
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... Write-only Read/Write Read/Write Read-only Write-only Read-only Write-only Read/Write E R NHANCED EGISTERS Read/Write Read/Write Read/Write Read/Write Read/Write Read-only 22 ST16C654/654D REV. 5.0.0 Table 9 C RITE OMMENTS LCR[ LCR[ LCR 0xBF LCR[ LCR 0xBF LCR[ LCR[ LCR[ LCR[ LCR[ LCR[ LCR = 0xBF LCR = 0xBF LCR = 0xBF ...
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... ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO REV. 5.0.0 T 10: INTERNAL REGISTERS DESCRIPTION. ABLE DDRESS EG EAD A2- AME RITE RHR RD Bit THR WR Bit IER RD/WR 0/ CTS# Int. Enable ISR RD FIFOs Enabled FCR WR RX FIFO Trigger ...
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... Bit-6 Bit-5 Bit-4 Bit-3 Bit-6 Bit-5 Bit-4 Bit-3 Bit-6 Bit-5 Bit-4 Bit-3 Bit-6 Bit-5 Bit-4 Bit-3 RX- RX- RX- TX- RDYC# RDYB# RDYA# RDYD# 24 ST16C654/654D REV. 5.0.0 EFR B -4 OMMENT Soft- Soft- Soft- ware ware ware Flow Flow Flow ...
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... IER versus Receive/Transmit FIFO Polled Mode Operation When FCR BIT-0 equals a logic 1 for FIFO enable; resetting IER bits 0-3 enables the ST16C654 in the FIFO polled mode of operation. Since the receiver and transmitter have separate bits in the LSR either or both can be used in the polled mode by selecting respective transmit or receive control bit(s). ...
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... MSR interrupt is cleared by a read to the MSR register. Xoff interrupt is cleared by a read to ISR. Special character interrupt is cleared by a read to ISR register or after next character is received. RTS# and CTS# flow control interrupts are cleared by a read to the MSR register. 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO 26 ST16C654/654D REV. 5.0.0 ...
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... ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO REV. 5.0 ABLE P ISR R RIORITY EGISTER EVEL ISR[0]: Interrupt Status Logic interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt service routine ...
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... EFR bit-4 Table 12 R FIFO T L ECEIVE RIGGER R ECEIVE FCR FCR T RIGGER - BIT L EVEL ST16C654/654D REV. 5.0.0 shows the complete selections. S EVEL ELECTION T RANSMIT T RIGGER L EVEL ...
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... ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO REV. 5.0.0 4.6 Line Control Register (LCR) - Read/Write The Line Control Register is used to specify the asynchronous data communication format. The word or character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register ...
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... Loopback Mode, this bit is used to write the state of the modem RI# interface signal. 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO T 13: P ABLE ARITY SELECTION -5 LCR B -4 LCR ARITY SELECTION parity 0 1 Odd parity 1 1 Even parity 0 1 Force parity to mark Forced parity to space, “0” 30 ST16C654/654D REV. 5.0.0 “1” ...
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... ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO REV. 5.0.0 MCR[3]: INT Output Enable Enable or disable INT outputs to become active or in three-state. This function is associated with the INTSEL input, see below table for details. This bit is also used to control the OP2# signal during internal loopback mode ...
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... MSR[0]: Delta CTS# Input Flag Logic change on CTS# input (default). Logic 1 = The CTS# input has changed state since the last time it was monitored. A modem status interrupt will be generated if MSR interrupt is enabled (IER bit-3). 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO 32 ST16C654/654D REV. 5.0.0 ...
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... ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO REV. 5.0.0 MSR[1]: Delta DSR# Input Flag Logic change on DSR# input (default). Logic 1 = The DSR# input has changed state since the last time it was monitored. A modem status interrupt will be generated if MSR interrupt is enabled (IER bit-3). ...
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... Receiver compares Xon1 or Xon2, Xoff1 or Xoff2 1 1 Transmit Xon1 and Xon2, Xoff1 and Xoff2, Receiver compares Xon1 and Xon2, Xoff1 and Xoff2 transmit flow control, Receiver compares Xon1 and Xon2, Xoff1 and Xoff2 34 ST16C654/654D REV. 5.0 ECEIVE OFTWARE LOW ONTROL ...
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... FIFO Status Register (FSTAT) - Read/Write This register is applicable only to the 100 pin QFP ST16C654. The FIFO Status Register provides a status indication for each of the transmit and receive FIFO. These status bits contain the inverted logic states of the TXRDY# A-D outputs and the (un-inverted) logic states of the RXRDY# A-D outputs. The contents of the FSTAT register are placed on the data bus when the FSRS# pin (pin 76 logic 0 ...
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... Bits 3-0 = Logic 0 Bits 7-4 = Logic levels of the inputs inverted Bits 7-0 = 0xFF Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0xFF RESET STATE Logic 1 Logic 0 Logic 1 Logic 1 Logic 1 Logic 0 ST16C654 = Three-State Condition ST16C654D = Logic 0 Three-State Condition (68 mode, INTSEL = 0) 36 ST16C654/654D REV. 5.0.0 ...
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... ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO REV. 5.0.0 ABSOLUTE MAXIMUM RATINGS Power Supply Range Voltage at Any Pin Operating Temperature Storage Temperature Package Dissipation TYPICAL PACKAGE THERMAL RESISTANCE DATA Thermal Resistance (64-TQFP) Thermal Resistance (68-PLCC) Thermal Resistance (100-QFP) ELECTRICAL CHARACTERISTICS DC ELECTRICAL CHARACTERISTICS ...
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... TO 5.5V QUAD UART WITH 64-BYTE FIFO FOR INDUSTRIAL GRADE PACKAGE L IMITS 3 ST16C654/654D REV. 5.0 2.97 5. IMITS 5 NIT ONDITIONS MHz ...
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... ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO REV. 5.0.0 AC ELECTRICAL CHARACTERISTICS TA (-40 + YMBOL ARAMETER T Delay From IOR# To Reset Interrupt RRI T Delay From Start To Interrupt SI T Delay From Initial INT Reset To Transmit Start INT T Delay From IOW# To Reset Interrupt ...
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... & < ST16C654/654D REV. 5.0.0 & & ...
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... ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO REV. 5.0 IGURE ODE NTEL ATA $ $ & 18 IGURE ODE OTOROLA $ $ & RITE IMING FOR HANNELS ...
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... ST16C654/654D REV. 5.0.0 A A-D HANNELS ' ' ...
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... ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO REV. 5.0 & I IGURE RANSMIT EADY NTERRUPT > ...
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... 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO T [FIFO M , DMA E IMING ODE NABLED ' ' ' ' ST16C654/654D REV. 5.0 A-D FOR HANNELS ...
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... ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO REV. 5.0 & I IGURE RANSMIT EADY NTERRUPT < 25 & I IGURE RANSMIT EADY NTERRUPT > ...
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... TO 5.5V QUAD UART WITH 64-BYTE FIFO INCHES MILLIMETERS MIN MAX MIN 0.055 0.063 1.40 0.002 0.006 0.05 0.053 0.057 1.35 0.007 0.011 0.17 0.004 0.008 0.09 0.465 0.480 11.80 0.390 0.398 9.90 0.020 BSC 0.50 BSC 0.018 0.030 0. ST16C654/654D REV. 5.0 MAX 1.60 0.15 1.45 0.27 0.20 12.20 10.10 0.75 7 ...
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... ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO REV. 5.0.0 68 LEAD PLASTIC LEADED CHIP CARRIER (PLCC Note: The control dimension is the inch column SYMBOL INCHES ...
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... INCHES MILLIMETERS MIN MAX MIN 0.102 0.134 2.60 0.002 0.014 0.05 0.100 0.120 2.55 0.009 0.015 0.22 0.004 0.009 0.11 0.931 0.951 23.65 0.783 0.791 19.90 0.695 0.715 17.65 0.547 0.555 13.90 0.0256 BSC 0.65 BSC 0.029 0.040 0. ST16C654/654D REV. 5.0 MAX 3.40 0.35 3.05 0.38 0.23 24.15 20.10 18.15 14.10 1.03 7 ...
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... ST16C654/654D REVISION HISTORY D R ATE EVISION October 2003 Rev 5.00 Changed to standard style single-column format. Text descriptions were clarified and simplified (eg. DMA operation, FIFO mode vs. Non-FIFO mode operations etc). Clarified timing diagrams. Renamed Rclk (Receive Clock) to Bclk (Baud Clock) and timing symbols. Added T ...
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... TO 5.5V QUAD UART WITH 64-BYTE FIFO GENERAL DESCRIPTION................................................................................................. 1 F ..................................................................................................................................................... 1 EATURES A ............................................................................................................................................... 1 PPLICATIONS F 1. ST16C654 B D IGURE LOCK IAGRAM IGURE IN UT SSIGNMENT IGURE IN UT SSIGNMENT OR ................................................................................................................................ 3 ORDERING INFORMATION PIN DESCRIPTIONS ......................................................................................................... 4 1.0 PRODUCT DESCRIPTION .................................................................................................................... 8 2 ...
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... ST16C654/654D REV. 5.0.0 4.4.1 INTERRUPT GENERATION: ...................................................................................................................................... 26 4.4.2 INTERRUPT CLEARING: ........................................................................................................................................... 26 4.5 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY ...................................................................................... ABLE NTERRUPT OURCE AND T 12 FIFO T ABLE RANSMIT AND ECEIVE 4.6 LINE CONTROL REGISTER (LCR) - READ/WRITE ...................................................................................... 29 4.7 MODEM CONTROL REGISTER (MCR) OR GENERAL PURPOSE OUTPUTS CONTROL - READ/WRITE 30 T 13: P ........................................................................................................................................................ 30 ...