gm82c765b ETC-unknow, gm82c765b Datasheet - Page 2

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gm82c765b

Manufacturer Part Number
gm82c765b
Description
Floppy Disk Subsystem Controller
Manufacturer
ETC-unknow
Datasheet

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DACK
LDOR
LDCR
WR
AO
DB0
DB1
DB2
DB3
DB4
DB5
DB7
DMA
RDD
1. Pin Descriptions
(condinued on next page)
TC
DB6
CS
RD
IRQ
RST
Pin Configuration
DIP
1
2
3
4
5
PIN NO
PLCC
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
16
17
18
19
20
1
2
3
4
5
GM82C765B
MNEMOMIC
A0
CS
RD
WR
DACK
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
ADDRESS LINE
CHIP
SIGNAL NAME
READ
WRITE
DMA
ACKNOWLEDG
VCC
IDX
TROO
WP
RPM, RWC
HDL
MO2. DS4
MO1, DS3
DS2
VSS
DS1
STEP
DIRC
WD
WE
HS
PCVAL
CLK1
CLK2
DRV
SELECT
DCHG
TROO
CACK
VCC
IDX
WR
CS
A0
RD
WP
TC
E
I/O
I
ST
I
ST
I
ST
I
ST
2
40
41
42
43
44
1
2
3
4
5
6
Control Signal for transfer of data or status onto the
data bus by the GM82C765B
Control signal for latching data form the bus into the
GM82C765B buffer register.
Selected when 0 (Low) allowing
operation from the host
Address line selecting data (=1) or status (=0)
information
(A0 = Logic 0 during
Used by the DMA Controller to transfer data from
the GM82C765B onto the bus. Logical equivalent to
signal is qualified by DMAEN from the Operation
Register.
CS
DBO
39
7
DB1
and A0=1. In special or PC AT mode, this
38
8
37
DB2
9 10 11 12 13 14 15 16 17
DB3
36
GM82C765B PL
DB4
35
34
DB5
DB6
33
FUNCTION
32
DB7
WR
DMA
31
IRQ
30
is illegal)
DCHGEN
29
28
27
26
25
24
23
22
20
19
18
21
GM82C765B
RD
PCVAL
XT1
XT1
DRV
XT2
RDD
RST
LDCR
HS
XT2
LDOR
or
WR

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