SI2404 SILABS [Silicon Laboratories], SI2404 Datasheet - Page 65

• Manufacturer Part Number: SI2404
• Description: V.90, V.34, V.32BIS, V.22BIS ISOMODEM WITH GLOBAL DAA
• Manufacturer: SILABS [Silicon Laboratories]

Parallel Interface 1 (0x01)
Reset settings = 0110_0011
Name
Type
Bit
Bit
7
6
5
4
3
2
1
0
Name
INTM
RXF
REM
ESC
RXF
TXE
RTS
CTS
INT
D7
R
TXE
Receive FIFO Almost Full (status).
0 = Receive FIFO (12 deep) contains three or more empty locations (RXF ≤ 9). The host can
clear the RXF interrupt without emptying the RX FIFO by writing a 0 to the RXF bit. This will
disable the RXF interrupt until the host has emptied the FIFO.
1 = Receive FIFO contains two or less empty locations (RXF ≥ 10).
Transmit FIFO Almost Empty (status).
0 = Transmit FIFO (14 deep) contains three or more characters (TXF ≥ 3).
1 = Transmit FIFO contains two or less characters (TXF ≤ 2).
Note: TXE interrupt will not trigger if the CTS bit is inactive. Therefore, the host does not need to poll
Receive FIFO Empty.
0 = Receive FIFO has valid data.
1 = Receive FIFO empty.
Note: If the interim timer (see PTMR - U6F, bits 7:0) set by PTMR expires, it will cause an interrupt. This
Interrupt Mask.
0 = In parallel mode, the INT pin is triggered by a rising edge on RXF or TXE only (default).
1 = In parallel mode, the INT pin is triggered by a rising edge on RXF, TXE, or INT.
Interrupt.
0 = No interrupt has occurred.
1 = Indicates that an interrupt (CID, OCD, PPD, RI, or DCD from U70) has occurred. This bit
is cleared via the AT:I command.
Escape.
Operation of this bit in parallel mode is functionally equivalent to the ESC pin in serial mode.
Request-to-Send.
Operation of this bit in parallel mode is functionally equivalent to the RTS pin in serial mode.
Use of the CTS and RTS bits (as opposed to the TXE and RXF bits) allows the flow control
between the host and the ISOmodem® to operate 1 byte at a time, rather than in blocks.
Clear-to-Send.
Operation of this bit in parallel mode is functionally equivalent to the CTS pin in serial mode.
Use of the CTS and RTS bits (as opposed to the TXE and RXF bits) allows the flow control
between the host and the ISOmodem to operate 1 byte at a time, rather than in blocks.
D6
R
CTS while waiting for transmit FIFO to empty. TXE can be cleared by writing it to 0.
interrupt will not set RXF, TXE, or INT. The interrupt handler on the host should then verify that
REM = 0 and begin to empty the receive FIFO (Parallel Interface 0 register) until REM = 1.
REM
D5
R
INTM
R/W
D4
INT
D3
R
Rev. 1.0
ESC
R/W
D2
Function
RTS
R/W
D1
Si2457/34/15/04
CTS
D0
R
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