x25640 Intersil Corporation, x25640 Datasheet
x25640
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x25640 Summary of contents
Page 1
... HOLD input, the X25640 will ignore transitions on its inputs, thus allowing the host to service higher priority interrupts. The WP input can be used as a hardwire input to the X25640 disabling all write attempts to the status register, thus providing a mechanism for limiting end user capability of altering 0, 1/4, 1/2 or all of the memory. ...
Page 2
... The WP pin function is blocked when the WPEN bit in the status register is LOW. This allows the user to install the X25640 in a system with WP pin grounded and still be able to write to the status register. The WP pin functions will be enabled when the WPEN bit is set “1”. ...
Page 3
... WEL and WIP are read-only and automatically set by other operations. The Write-In-Process (WIP) bit indicates whether the X25640 is busy with a write operation. When set to a “1”, a write is in progress, when set to a “0”, no write is in progress. During a write, all other bits are set to “1”. ...
Page 4
... CS must go LOW and remain LOW for the duration of the operation. The host may continue to write bytes of data to the X25640. The only restriction is the 32 bytes must reside on the same page. If the address counter reaches the end of the page and the clock contin- ues, the counter will “ ...
Page 5
... X25640 Operational Notes The X25640 powers-up in the following state: • The device is in the low power standby state. • A HIGH to LOW transition required to enter an active state and receive an instruction. • SO pin is high impedance. • The “write enable” latch is reset. ...
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... X25640 Figure 3. Write Enable Latch Sequence CS SCK SI SO Figure 4. Byte Write Operation Sequence SCK INSTRUCTION SI HIGH IMPEDANCE HIGH IMPEDANCE BIT ADDRESS 3089 ILL F05 ...
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... X25640 Figure 5. Page Write Operation Sequence SCK INSTRUCTION SCK DATA BYTE Figure 6. Write Status Register Operation Sequence CS 0 SCK SI HIGH IMPEDANCE ...
Page 8
... –0 5V. CC Test is stable until the specified operation can be initiated. These parameters CC 8 Limits X25640 5V 10% Test Conditions SCK = V x 0.1/V x 0.9 @ 1MHz Open 5. –0.4mA OH ...
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... X25640 EQUIVALENT A.C. LOAD CIRCUIT 2.16K OUTPUT 3.07K A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified) Data Input Timing Symbol Parameter f Clock Frequency SCK t Cycle Time CYC CS Lead Time t LEAD CS Lag Time t LAG t Clock HIGH Time WH t Clock LOW Time WL t Data Setup Time ...
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... X25640 Serial Output Timing CS SCK MSB OUT ADDR SI LSB IN Serial Input Timing CS t LEAD SCK MSB IN HIGH IMPEDANCE CYC MSB–1 OUT LAG DIS LSB OUT 3089 ILL F10 LAG t FI LSB IN ...
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... X25640 Hold Timing CS SCK SO SI HOLD 3089 ILL F12.1 ...
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... X25640 PACKAGING INFORMATION HALF SHOULDER WIDTH ON ALL END PINS OPTIONAL 0.015 (0.38) TYP. 0.010 (0.25) NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH 8-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P 0.430 (10.92) 0.360 (9.14) PIN 1 INDEX PIN 1 0.300 (7.62) REF. SEATING PLANE 0.150 (3.81) 0.125 (3.18) ...
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... X25640 PACKAGING INFORMATION 14-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S PIN 1 INDEX PIN 1 0.014 (0.35) 0.020 (0.51) (4X) 7 0.050 (1.27) 0.010 (0.25) 0.020 (0.50) 0 – 8 0.016 (0.41) 0.037 (0.937) NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 0.150 (3.80) 0.158 (4.00) 0.336 (8.55) 0.345 (8.75) 0.004 (0.10) 0.010 (0.25 0.0075 (0.19) 0.250" 0.010 (0.25) FOOTPRINT 13 0 ...
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... Temperature Range Blank = Commercial = + Industrial = – + Military = – +125 C Package P = 8-Lead Plastic DIP S = 14-Lead SOIC X25640 8-Lead Plastic DIP S = 14-Lead SOIC X Blank = 10%, – + 10%, –55 ºC to +125 ºC ...