msm6722gs-k Oki Semiconductor, msm6722gs-k Datasheet - Page 13

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msm6722gs-k

Manufacturer Part Number
msm6722gs-k
Description
Pitch Control Ic For The Speech Signal
Manufacturer
Oki Semiconductor
Datasheet

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Pitch-Control Circuit
[BINARY mode] (P3, P2, P1, P0)
As shown in the diagram below, this IC has an internal prevention circuit for approximately 62
ms of chattering . Therefore, hold these pins at "H" level for 62 ms or more. P3, P2, P1, and P0 pins
are used to directly set the pitch steps.
Sixteen pitch steps are provided, but step 16 cannot be set.
[UP/DOWN mode] (UPC, DWC, PRST)
As shown in the diagram below, this IC has an internal prevention circuit for approximately 62
ms of chattering . Therefore, hold these pins at "H" level for 62 ms or more.
Inputting a "H" level pulse to the UPC pin raises the pitch by one step, and inputting a "H" level
pulse to the DWC pin lowers the pitch by one step. Inputting a "H" level pulse to the PRST pin
or to the UPC and DWC pins at the same time sets the no-pitch change state (pitch step 8).
[BINARY mode]
[UP/DOWN mode]
Pulse
input
Valid
data
PRST
DWC
UPC
P3
P2
P1
P0
Pitch-Control Circuit
prevention
prevention
Chattering
Chattering
circuit
circuit
To pitch register
To pitch register
MSM6722
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