tfdu6108 Vishay, tfdu6108 Datasheet - Page 11

• Manufacturer Part Number: tfdu6108
• Description: Fast Infrared Transceiver Module 4 Mbit/s , Irda Serial Interface Compatible, 2.7 V To 5.5 V Supply Voltage Range
• Manufacturer: Vishay

Functional description
The serial interface is designed to interconnect two or
more devices. One of the devices is always in control
of the serial interface and is responsible for starting
every transaction. This device functions as the bus
master and is always the infrared controller. The infra-
red transceivers act as bus slaves and only respond
to transactions initiated by the master. A bus transac-
tion is made up of one or two phases. The first phase
is the Command Phase and is present in every trans-
action. The second phase is the Response Phase
and is present only in those transactions in which data
must be returned from the slave. If the operation
involves a data transfer from the slave, there will be a
Response Phase following the Command Phase in
which the slave will output the data.
The Response Phase, if present, must begin 4 clock
cycles after the last bit of the Command Phase, as
shown in figures 1 - 7 and 1 - 8, otherwise it is
assumed that there will be no response phase and the
master can terminate the transaction.
The SCLK line is always driven by the master and is
used to clock the data being written to or read from
the slave.
This line is driven by a totem-pole output buffer. The
SCLK line is always stopped when the serial interface
is idle to minimize power consumption and to avoid
any interference with the analog circuitry inside the
slave. There are no gaps between the bytes in either
the Command or Response Phase. Data is always
transferred in Little Endian order (least significant bit
first). Input data is sampled on the rising edge of
SCLK. IRTX/SWDAT output data from the controller
is clocked by SCLK falling edge. IRRX/SRDAT output
data from the slave is clocked by SCLK rising edge.
Each byte of data in both Command and Response
Phases is preceded by one start bit. The data to be
written to the slave is carried on the IRTX/SWDAT
line. When the control interface is idle, this line carries
the infrared data signal used to drive the transmitter
LED. When the first low-to-high transition on SCLK is
detected at the beginning of the command sequence,
the slave will disable the transmitter LED. The infrared
controller then outputs the command string on the
IRTX/SWDAT line. On the last SCLK cycle of the
command sequence the slave re-enables the trans-
mitter LED and normal infrared transmission can
resume. No transition on SCLK must occur until the
next command sequence otherwise the slave will dis-
able the transmitter LED again. Read data is carried
on the IRRX/SRDAT line. The slave disables the
internal signal from the receiver photo diode during
Document Number 82537
Rev. 1.7, 13-May-05
the response phase of a read transaction. The
addressed slave will output the read data on the
IRRX/SRDAT line regardless of the setting of the
Receiver Output Enable bit in the Mode Selection reg-
ister 0. Non addressed slaves will tri-state the IRRX/
SRDAT line. When the transceiver is powered up, the
IRTX/SWDAT line should be kept low and SCLK
should be cycled at least 30 times by the infrared con-
troller before the first command is issued on the IRTX/
SWDAT line. This guarantees that the transceiver
interface circuitry will properly initialize and be ready
to receive commands from the controller. In case of a
multiple transceiver configuration, only one trans-
ceiver should have the receiver output enabled. A
series resistor (approx. 200 ohms) should be placed
on the receiver output from each transceiver to pre-
vent large currents in case a conflict occurs due to a
programming error.
(INTERNAL SIGNAL)
(INTERNAL SIGNAL)
(INTERNAL SIGNAL)
SCLK
IRTX/
SWDAT
IRRX/
SRDAT
TLED_DIS
SCLK
IRTX/
SWDAT
IRRX/
SRDAT
TLED_DIS
RES
Figure 8. Special Command Waveform
(Note 1)
Figure 7. Initial Reset Timing
Vishay Semiconductors
TFDU6108
www.vishay.com
17176
17175
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