EL4583C Elantec Semiconductor, Inc. (acquired by Intersil), EL4583C Datasheet
EL4583C
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EL4583C Summary of contents
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... The EL4583C sync slice level is set to the mid-point between sync tip and the blanking level. This 50% point is determined by two internal sample and hold circuits that track sync tip and back porch levels. It provides hum and noise rejection and compensates for input levels of 0 ...
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... EL4583C Sync Separator, 50% Slice, S-H, Filter, H Absolute Maximum Ratings V Supply CC Storage Temperature Pin Voltages Important Note: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: T ...
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... Vertical pulse width in absence of serrations on input signal Sync Separator, 50% Slice, S-H, Filter 25° 15pF -1.6mA Description [3] = 3.6MHz (Pin 4)—Comp Sync p-p /V BLANK Pin 4 p-p, = 0.8V; vertical is 3H lines wide of NTSC signal OH 3 EL4583C OUT = 1.6mA OL Min Typ Max Unit 3.8 5 6.2 µs 195 µs 2.7 3.7 4.7 µ 250 400 ns 0 ...
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... EL4583C Sync Separator, 50% Slice, S-H, Filter, H Pin Descriptions Pin No. Pin Name 1 Filter Cut-Off A resistor RF connected between this input and ground determines the input filter characteristic. Increasing RF increases the filter 3.58MHz color burst attenuation. See the typical performance characteristics. 2 Set Detect Level A resistor RLV connected between pin 2 and ground determines the value of the minimum signal which triggers the loss of signal output on pin 10 ...
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... Level Out (Pin 9) vs Sync. Tip Amplitude Package Power Dissipation vs Ambient Temp. JEDEC JESD51-3 Low Effective Thermal Conductivity Test Board 1.8 1.54W 1.6 1.4 1.136W 1.2 1 0.8 0.6 0.4 0 Ambient Temperature (°C) 5 EL4583C OUT Vertical Default Delay Time vs RSET Minimum Signal Detect vs RLV 75 85 100 125 150 ...
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... EL4583C Sync Separator, 50% Slice, S-H, Filter, H Timing Diagram Notes: b. The composite sync output reproduces all the video input sync pulses, with a propagation delay. c. Vertical sync leading edge is coincident with the first vertical serration pulse leading edge, with a propagation delay. d. Odd-even output is low for even field, and high for odd field. ...
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... Sync Separator, 50% Slice, S-H, Filter, H Figure 2. Figure 3. 7 EL4583C OUT ...
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... EL4583C Sync Separator, 50% Slice, S-H, Filter, H Figure 4. Standard (NTSC Input) H. Sync Detail OUT 8 ...
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... The internal timing circuits are referenced to I and V , the timout period being inversely proportional R3 to the timing current. The vertical output pulse is started on the first serration pulse in the vertical interval and is ) with high REF 9 EL4583C OUT with op-amp A2 forces pin The internal resis- TR which ...
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... EL4583C Sync Separator, 50% Slice, S-H, Filter, H then self-timed out. In the absence of a serration pulse, an internal timer will default the start of vertical. The Horizontal circuit senses C/S edges and produces the true horizontal pulses of nominal width 5µs. The leading edge is triggered from the leading edge of the input H sync, with the same prop ...
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... Block Diagram Figure 5. Standard (NTSC Input) H. Sync Detail Sync Separator, 50% Slice, S-H, Filter Note: RSET must resistor 11 EL4583C OUT ...
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... EL4583C Sync Separator, 50% Slice, S-H, Filter, H General Disclaimer Specifications contained in this data sheet are in effect as of the publication date shown. Elantec, Inc. reserves the right to make changes in the cir- cuitry or specifications contained herein at any time without notice. Elantec, Inc. assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement ...