UPD4702C NEC [NEC], UPD4702C Datasheet - Page 3

• Manufacturer Part Number: UPD4702C
• Description: INCREMENTAL ENCODER 8-BIT UP/DOWN COUNTER CMOS INTEGRATED CIRCUITS
• Manufacturer: NEC [NEC]

1. DESCRIPTION OF OPERATIONS
(1) Count operation
phase pulses. Therefore, a count operation is performed by an A input edge and a B input edge.
(2) Latch operation
“H” to “L” during a count operation, the internal latch signal STB remains at “H” until the end of the count operation.
Therefore, the count value is latched correctly even if STB input is performed asynchronously from the A and B input
(if STB changes from “H” to “L” within t
either the pre-count or post-count value). However, when a PD4704 is added, the correct value cannot be latched
if all digits are latched simultaneously when a carry or borrow is generated (the high-order digit may be latched
before carry/borrow transmission).
Count Operation
The PD4702 incorporates a phase discrimination circuit, and counts by 4-multiplication of the A and B input 2-
An R-S flip-flop is inserted in the strobe input of the latch circuit as shown in Fig. 2, and when STB changes from
A Input
B Input
1
A, B Inputs
STB
STB
Latched
when L
Forward (Up-Count)
2
Fig. 1 Count Operation Timing Chart
3
SABSTB
If t
is input to the latch.
SABSTB
Fig. 2 STB Input Circuit
4
(40 ns) after the A input or B input edge, the latch contents will be
From Phase Discrimination Circuit
(Count Pulse)
is 40 ns or longer, the post-count value
5
t
SABSTB
4
STB
Reverse (Down-Count)
3
2
1
0
PD4702
3