gl846 Genesys Logic, gl846 Datasheet - Page 56

• Manufacturer Part Number: gl846
• Description: High Speed Usb 2.0 2-in-1 Scanner Controller With Fast Adf
• Manufacturer: Genesys Logic

©2000-2007 Genesys Logic Inc. - All rights reserved.
Offset 7Bh ……..……..………………..……..…..….………..….………..…..…. Default value = 8’h00
Offset 7Ch ……..……..……………..………....….………..….………..…..…. Default value = 8’h00
Offset 7Dh ……..……..………………..………..…………..….………..…..…. Default value = 8’h00
Offset 7Eh ……..……..………………..………..…………..….………..…..…. Default value = 8’h00
CK4MAP15 CK4MAP14 CK4MAP13 CK4MAP12 CK4MAP11 CK4MAP10 CK4MAP9 CK4MAP8
7-0 CK4MAP [15:8] Bits mapping setting for CCD clock 4.
7-0 CK4MAP[7:0] Bits mapping setting for CCD clock 4.
GPOLED25 GPOLED24 GPOLED23 GPOLED22 GPOLED21 GPOLED10 GPOLED9 GPOLED8
CK4MAP7 CK4MAP6 CK4MAP5 CK4MAP4 CK4MAP3 CK4MAP2 CK4MAP1 CK4MAP0
CK1NEG
7 CK1NEG
6 CK3NEG
5 CK4NEG
4 RSNEG
3 CPNEG
2 BSMPNEG
1 VSMPNEG
0 DLYSET
7 GPOLED25
6 GPOLED24
5 GPOLED23
4 GPOLED22
3 GPOLED21
R/W
R/W
R/W
R/W
GL846 High Speed USB2.0 2-in-1 Scanner Controller With Fast ADF
CK3NEG
R/W
R/W
R/W
R/W
0 CCD clock1,clock2 output are synchronized with rising edge of system clock.
1 CCD clock1 & clock2 output are synchronized with falling edge of system clock.
0 CCD clock3 output is synchronized with rising edge of system clock.
1 CCD clock3 output is synchronized with falling edge of system clock.
0 CCD clock4 output is synchronized with rising edge of system clock.
1 CCD clock4 output is synchronized with falling edge of system clock.
0 CCD RS output is synchronized with rising edge of system clock.
1 RS output is synchronized with falling edge of system clock.
0 CCD CP output is synchronized with rising edge of system clock.
1 CCD CP output is synchronized with falling edge of system clock.
0 AFE video sample output is synchronized with rising edge of system clock.
1 AFE video sample output is synchronized with falling edge of system clock.
0 AFE dark sample output is synchronized with rising edge of system clock.
1 AFE dark sample output is synchronized with falling edge of system clock.
0 The function is disabled.
1 To enable VSMP and BSMP to delay output by 8.33ns unit. Please refer to Reg 7F.
0 Set GPIO25 as general purpose I/O.
1 Set GPIO25 as LED output.
0 Set GPIO24 as general purpose I/O.
1 Set GPIO24 as LED output.
0 Set GPIO23 as general purpose I/O.
1 Set GPIO23 as LED output.
0 Set GPIO22 as general purpose I/O.
1 Set GPIO22 as LED output.
0 Set GPIO21 as general purpose I/O.
CK4NEG
R/W
R/W
R/W
R/W
RSNEG
R/W
R/W
R/W
R/W
CPNEG
R/W
R/W
R/W
R/W
BSMPNEG VSMPNEG
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DLYSET
Page 56
R/W
R/W
R/W
R/W