DS2762 MAXIM [Maxim Integrated Products], DS2762 Datasheet - Page 15

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DS2762

Manufacturer Part Number
DS2762
Description
High-Precision Li+ Battery Monitor With Alerts
Manufacturer
MAXIM [Maxim Integrated Products]
Datasheet

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Table 2. Memory Map
* Each EEPROM block is read/write until locked by the LOCK command, after which it is read-only.
PROTECTION REGISTER
The protection register consists of flags that indicate protection circuit status and switches that give conditional
control over the charging and discharging paths. Bits OV, UV, COC, and DOC are set when corresponding
protection conditions occur and remain set until cleared by the host system. The default values of the CE and DE
bits of the protection register are stored in lockable EEPROM in the corresponding bits in address 30h. A recall
data command for EEPROM block 1 recalls the default values into CE and DE. Figure 10 shows the format of the
protection register. The function of each bit is described in detail in the following paragraphs.
Figure 10. Protection Register Format
ADDRESS (HEX)
09–0B
1A–1F
90–FF
02–06
12–17
20–2F
30–3F
40–7F
86-8F
0C
0D
0E
00
01
07
08
0F
10
11
18
19
80
81
82
83
84
85
BIT 7
OV
Protection Register
Status Register
Reserved
EEPROM Register
Special Feature Register
Reserved
Voltage Register MSB
Voltage Register LSB
Current Register MSB
Current Register LSB
Accumulated Current Register MSB
Accumulated Current Register LSB
Reserved
Temperature Register MSB
Temperature Register LSB
Reserved
EEPROM, block 0
EEPROM, block 1
Reserved
SRAM (Optional Accumulated Current Interrupt
High Threshold MSB)
SRAM (Optional Accumulated Current Interrupt
High Threshold LSB)
SRAM (Optional Accumulated Current Interrupt
Low Threshold MSB)
SRAM (Optional Accumulated Current Interrupt
Low Threshold LSB)
SRAM (Optional Temperature Interrupt High
Threshold)
SRAM (Optional Temperature Interrupt Low
Threshold)
SRAM
Reserved
BIT 6
UV
BIT 5
COC
DESCRIPTION
BIT 4
DOC
ADDRESS 00
15 of 25
BIT 3
CC
BIT 2
DC
READ/WRITE
BIT 1
CE
R/W*
R/W*
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
BIT 0
DE

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