CS42428 CIRRUS [Cirrus Logic], CS42428 Datasheet
CS42428
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CS42428 Summary of contents
Page 1
... The general purpose outputs may be driven high or low, or mapped to a variety of DAC mute con- trols or ADC overflow indicators. The CS42428 is ideal for audio systems requiring wide dynam- ic range, negligible distortion and low noise, such as A/V receivers, DVD receivers, digital speaker and automotive audio systems ...
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... C components of Cirrus Logic, Inc., or one of its sublicensed Associated Companies conveys a license under the Phillips I 2 those components in a standard I C system. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. 2 CS42428 2 C Patent Rights to use ...
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... ANALOG INPUT CHARACTERISTICS .................................................................................. 51 A/D DIGITAL FILTER CHARACTERISTICS .......................................................................... 52 ANALOG OUTPUT CHARACTERISTICS .............................................................................. 55 D/A DIGITAL FILTER CHARACTERISTICS .......................................................................... 56 SWITCHING CHARACTERISTICS ........................................................................................ 61 SWITCHING CHARACTERISTICS - CONTROL PORT - I2C FORMAT ............................... 62 SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT ............................... 63 DC ELECTRICAL CHARACTERISTICS ................................................................................ 64 DIGITAL INTERFACE CHARACTERISTICS ......................................................................... 64 7 PARAMETER DEFINITIONS ................................................................................................... 65 8 REFERENCES ......................................................................................................................... 66 9 PACKAGE DIMENSIONS .................................................................................................... 67 THERMAL CHARACTERISTICS ........................................................................................... 67 CS42428 ........................ 42 3 ...
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... Figure 45. Double Speed (slow) Transition Band.......................................................................... 59 Figure 46. Double Speed (slow) Transition Band (detail).............................................................. 59 Figure 47. Double Speed (slow) Passband Ripple........................................................................ 59 Figure 48. Quad Speed (fast) Stopband Rejection ....................................................................... 59 Figure 49. Quad Speed (fast) Transition Band.............................................................................. 59 Figure 50. Quad Speed (fast) Transition Band (detail).................................................................. 60 Figure 51. Quad Speed (fast) Passband Ripple............................................................................ 60 4 CS42428 ...
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... Table 8. ADC One_Line Mode ...................................................................................................... 35 Table 9. DAC One_Line Mode ...................................................................................................... 35 Table 10. RMCK Divider Settings ................................................................................................. 37 Table 11. OMCK Frequency Settings ........................................................................................... 38 Table 12. Master Clock Source Select.......................................................................................... 38 Table 13. PLL Clock Frequency Detection.................................................................................... 39 Table 14. Example Digital Volume Settings .................................................................................. 42 Table 15. ATAPI Decode .............................................................................................................. 44 Table 16. Example ADC Input Gain Settings ................................................................................ 45 CS42428 5 ...
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... SPI mode. AD0/CS 10 Address Bit the chip select signal in SPI mode. INT 11 Interrupt (Output ) - The CS42428 will generate an interrupt condition as per the Interrupt Mask register. See “Interrupts” on page 28 for more details ...
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... ADC Serial Data Output ( Output ) - Output for two’s complement serial audio PCM data from the output of the internal and external ADCs. ADCIN1 58 External ADC Serial Input ( Input ) - The CS42428 provides for up to two external stereo analog to digital ADCIN2 57 converter inputs to provide a maximum of six channels on one serial data output line when the CS42428 is placed in One Line mode ...
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... AD0/CS VQ FILT+ 6 REFGND VLC 0.1 µF LPFLT AGND AGND DGND DGND Connect DGND and AGND at single point near Codec Figure 1. Typical Connection Diagram CS42428 +5 V 0.01 µF 0.1 µ µF 0.01 µF 0.1 µ µ Analog Conditioning 37 and Muting 35 Analog Conditioning 34 and Muting ...
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... REFGND VLC 39 0.1 µF LPFLT DGND DGND AGND AGND Connect DGND and AGND at single point near Codec CS42428 +5 V 0.1 µ µF 0.1 µ µF Analog Conditioning and Muting Analog Conditioning and Muting Analog Conditioning and Muting Analog Conditioning and Muting Analog Conditioning ...
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... All functions are configured through a serial control port operable in SPI mode mode. Figure 1 shows the recommended connections for the CS42428. The CS42428 operates in one of three oversampling modes based on the input sample rate. Mode selection is determined by the FM bits in register “Functional Mode (address 03h)” on page 33. Single-Speed mode (SSM) supports input sample rates kHz and uses a 128x oversampling ratio ...
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... This feature makes it possible to perform a system DC offset calibration by: 1) Running the CS42428 with the high pass filter enabled until the filter settles. See the Digital Filter Characteristics for filter settling time. 2) Disabling the high pass filter and freezing the stored DC offset. ...
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... The CS42428 is a linear phase design and does not include phase or amplitude compensation for an exter- nal filter. Therefore, the DAC system phase and amplitude response will be dependent on the external an- alog circuitry. Figure 4 shows the full-scale analog output levels. AOUT+ AOUT- 3.3.2 Interpolation Filter To accommodate the increasingly complex requirements of digital audio systems, the CS42428 incorpo- rates selectable interpolation filters for each mode of operation. A “ ...
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... Purpose Pin Control (addresses 29h to 2Fh)” on page 48. 3.3.4 ATAPI Specification The CS42428 implements the channel mixing functions of the ATAPI CD-ROM specification. The ATAPI functions are applied per A-B pair. Refer to Table 15 on page 44 and Figure 5 for additional infor- mation. ...
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... Clock Generation The clock generation for the CS42428 is shown in the figure below. The internal MCLK is derived from the output of the PLL or a master clock source attached to OMCK. The mux selection is controlled by the SW_CTRLx bits and can be configured to manual switch mode only, or automatically switch on loss of PLL lock to the other source input ...
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... OMCK or must be synchronous to the supplied ADC_LRCK used as the input to 10 2700 680 Table 1. PLL External Component Values OMCK (MHz) Double Speed (50 to 100 kHz) 512x 128x 192x - - - - 12.2880 18.4320 24.5760 - - - - Table 2. Common OMCK Clock Frequencies CS42428 11 ms Quad Speed (100 to 192 kHz) 256x 64x 96x 128x - - - - - - - - 12.2880 18.4320 24.5760 15 ...
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... The Left/Right clock (ADC_LRCK or DAC_LRCK) is used to indicate left and right data frames and the start of a new sample period. It may be an output of the CS42428 (master mode may be generated by an external source (slave mode). As described in later sections, particular modes of operation do allow the sample rate, Fs, of the ADC_SP and the DAC_SP to be different, but must be multiples of each other ...
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... DAC #7 right channel DAC #8 one line mode DAC channels 7,8 left channel ADC #1 right channel ADC #2 one line mode ADC channels 1,2,3,4,5,6 left channel External ADC #3 right channel External ADC #4 left channel External ADC #5 right channel External ADC #6 CS42428 17 ...
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... Slave 48, 64, 128 Fs single-speed mode 64 Fs double-speed mode 64 Fs quad-speed mode 64, 128 Fs single-speed mode 64 Fs double-speed mode 64 Fs quad-speed mode Figure 7. Right Justified Serial Audio Formats CS42428 R ight C han nel Notes 0 ...
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... Fs double-speed mode 32 quad-speed mode 48, 64, 128 Fs single-speed mode 64 Fs double-speed mode 64 Fs quad-speed mode Figure 9. Left Justified Serial Audio Formats CS42428 MSB LSB Notes Righ t C han ...
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... AC2 24 clks 24 clks 24 clks D AC8 24 clks DC2 24 clks 24 clks 24 clks SCLK Rate(s) Slave not supported single-speed mode CS42428 64 clks Right Channel LSB M SB LSB M SB LSB DAC4 D AC6 20 clks 20 clks A DC4 A DC6 20 clks 20 clks Notes 128 clks ...
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... Figure 12. ADCIN1/ADCIN2 Serial Audio Format For proper operation, the CS42428 must be configured to select which SCLK/LRCK is being used to clock the external ADCs. The EXT ADC SCLK bit in register “Misc Control (address 05h)” on page 36, must be set accordingly. Set this bit to ‘1’ if the external ADCs are wired using the DAC_SP clocks. If the ADCs are wired to use the ADC_SP clocks, set this bit to ‘ ...
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... DCIN1 64Fs,128Fs, 256Fs DAC_SCLK A DCIN2 DA C_LRCK ADC Data ADC_S DOUT DAC_SDIN1 DAC_SDIN2 DAC_SDIN3 DAC_SDIN4 CS42428 Figure 13. OLM Configuration #1 CS42428 Description DAC Mode One Line Mode #2 not valid not valid DAC_SCLK=256Fs DAC_LRCK=SSM ADC_SCLK=64Fs ADC_LRCK=DAC_LRCK MCLK S CLK _P ORT1 LRCK_PORT1 SDIN_PORT1 S CLK _P ORT2 ...
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... ADC IN2 64Fs,128Fs DA C_S CLK D AC_LRCK DAC _SD IN1 DAC _SD IN2 DAC _SD IN3 DAC _SD IN4 CS42428 Figure 14. OLM Configuration #2 CS42428 Description One Line Mode #2 not valid not valid not valid MCLK SC LK_PORT1 LRC K_PO _PO R T1 ...
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... One Line Mode #2 DAC_SCLK=256Fs DAC_LRCK=SSM ADC_SCLK=64Fs ADC_LRCK=SSM/DSM/QSM DAC_SCLK=256Fs DAC_LRCK=SSM ADC_SCLK=128Fs ADC_LRCK=SSM not valid MCLK 64Fs,128Fs SC LK_POR T1 LRC K_PO RT1 S DIN _PO RT1 64Fs,128Fs,256Fs SC LK_POR T2 LRC K_PO RT2 SDO UT1_P ORT2 SDO UT2_P ORT2 SDO UT3_P ORT2 SDO UT4_P ORT2 DIGITAL AUD IO PROCESSOR CS42428 ...
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... Fs SCLK_PO RT2 DAC_SCLK LRCK_PORT2 DAC_LRCK SDOUT1_PORT2 DAC_SDIN1 DAC_SDIN2 SDOUT2_PORT2 DAC_SDIN3 SDOUT3_PORT2 DAC_SDIN4 SDOUT4_PORT2 CS42428 DIGITAL AUDIO PRO CESSO R Figure 16. OLM Configuration #4 CS42428 Description clocks. ADC are supported One Line Mode #2 DAC_SCLK=256Fs DAC_LRCK=SSM ADC_SCLK=64Fs/128Fs ADC_LRCK=SSM/DSM/QSM not valid not valid 25 ...
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... SPI Mode In SPI mode the CS42428 chip select signal, CCLK is the control port bit clock (input into the CS42428 from the microcontroller), CDIN is the input data line from the microcontroller, CDOUT is the output data line to the microcontroller. Data is clocked in on the rising edge of CCLK and out on the falling edge ...
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... All other transitions of SDA occur while the clock is low. The first byte sent to the CS42428 after a Start condition consists bit chip address field and a R/W bit (high for a read, low for a write). The upper 5 bits of the 7-bit address field are fixed at 10011. To communicate with a CS42428, the chip address field, which is the first byte sent to the CS42428, should match 10011 followed by the settings of the AD1 and AD0 ...
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... Interrupts The CS42428 has a comprehensive interrupt capability. The INT output pin is intended to drive the inter- rupt input pin on the host microcontroller. The INT pin may be set to be active low, active high or active low with no active pull-up transistor. This last mode is used for active low, wired-OR hook-ups, with mul- tiple peripherals connected to the microcontroller interrupt input pin. Many conditions can cause an interrupt, as listed in the interrupt status register descriptions. See “ ...
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... When RST is low, the CS42428 enters a low power mode and all internal states are reset, including the control port and registers, and the outputs are muted. When RST is high, the control port becomes opera- tional and the desired settings should be loaded into the control registers ...
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... B3_VOL6 B3_VOL5 B3_VOL4 A4_VOL6 A4_VOL5 A4_VOL4 B4_VOL6 B4_VOL5 B4_VOL4 INV_A4 INV_B3 INV_A3 Reserved Reserved P1_ATAPI4 CS42428 Rev_ID3 Rev_ID2 Rev_ID1 Reserved ADC_CLK DAC_DEM SEL DAC_OL1 DAC_OL0 Reserved FILTSEL HPF_ DAC_SP FREEZE ...
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... Mode0 Polarity Function4 Mode0 Polarity Function4 Mode0 Polarity Function4 Mode0 Polarity Function4 Mode0 Polarity Function4 CS42428 P2_ATAPI3 P2_ATAPI2 P2_ATAPI1 P3_ATAPI3 P3_ATAPI2 P3_ATAPI1 P4_ATAPI3 P4_ATAPI2 P4_ATAPI1 LGAIN3 LGAIN2 LGAIN1 RGAIN3 RGAIN2 RGAIN1 ...
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... Chip I.D. and Revision Register (address 01h) (Read Only Chip_ID3 Chip_ID2 Chip_ID1 5.2.1 CHIP I.D. (CHIP_IDX) Default = 1110 Function: I.D. code for the CS42428. Permanently set to 1110. 5.2.2 CHIP REVISION (REV_IDX) Default = 0001 Function: CS42428 revision level. Revision C is coded as 0011 MAP5 MAP4 ...
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... Selects the required range of sample rates for all converters clocked from the DAC serial port (DAC_SP). Bits must be set to the corresponding sample rate range when the DAC_SP is in Master or Slave mode PDN_DAC4 PDN_DAC3 ADC_FM0 Reserved CS42428 2 1 PDN_DAC2 PDN_DAC1 PDN 2 1 ADC_SP SEL DAC_DEM Reserved 0 ...
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... The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and the options are detailed in Figures FRC_PLL_LK DE-EMPH[1:0] reg06h[0] reg1Eh[5: Table 6. DAC De-Emphasis ADC_OL0 DAC_OL1 CS42428 De-Emphasis Mode No De-Emphasis Auto-Detect Fs Reserved 32 kHz 44.1 kHz 48 kHz DAC_OL0 Reserved CODEC_RJ16 ...
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... Table 7. Digital Interface Formats Description DIF: take the DIF setting from reg04h[7:6] One-Line #1 One-Line #2 reserved Table 8. ADC One_Line Mode Description DIF: take the DIF setting from reg04h[7:6] One-Line #1 One-Line #2 reserved Table 9. DAC One_Line Mode CS42428 Format Figure Format Figure ...
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... When this bit is set, the internal high-pass filter for the selected channel will be disabled.The current DC offset value will be frozen and continue to be subtracted from the conversion result. See “A/D Dig- ital Filter Characteristics” on page 52 FREEZE FILT_SEL CS42428 2 1 HPF_FREEZE DAC_SP ADC_SP M/S 0 M/S ...
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... Divides/multiplies the internal MCLK, either from the PLL or OMCK, by the selected factor. RMCK_DIV1 RMCK_DIV0 OMCK Freq0 PLL_LRCK Description 0 0 Divide Divide Divide Multiply by 2 Table 10. RMCK Divider Settings CS42428 2 1 SW_CTRL1 SW_CTRL0 FRC_PLL_LK 0 37 ...
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... PLL LOCK TO LRCK (PLL_LRCK) Default = Disabled 1 - Enabled Function: When enabled, the internal PLL of the CS42428 will lock to the LRCK of the ADC serial port (ADC_LRCK) while the ADC_SP is in slave mode. 5.7.4 MASTER CLOCK SOURCE SELECT (SW_CTRLX) Default = 01 Function: These two bits, along with the UNLOCK bit in register “Interrupt Status (address 20h) (Read Only)” ...
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... Default = xxxh Function: The CS42428 will auto-detect the ratio between the OMCK and the recovered clock from the PLL, which is displayed in register 07h. Based on this ratio, the absolute frequency of the PLL clock can be determined, and this information is displayed according to the following table. If the absolute fre- quency of the PLL clock does not match one of the given frequencies, this register will display the closest available value ...
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... The zero cross function is independently monitored and implemented for each channel. 5.10.3 AUTO-MUTE (AMUTE) Default = Disabled 1 - Enabled Function SZC1 SZC0 AMUTE CS42428 2 1 MUTE ADC_SP RAMP_UP RAMP_DN 0 ...
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... The Digital-to-Analog converters of the CS42428 will mute the output following the reception of 8192 consecutive audio samples of static 0 or -1. A single sample of non-static data will release the mute. Detection and muting is done independently for each channel. The quiescent voltage on the output will be retained and the MUTEC pin will go active during the mute period ...
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... Decimal Value 120 180 Table 14. Example Digital Volume Settings INV_A3 INV_B2 Px_ATAPI4 Px_ATAPI3 CS42428 2 1 xx_VOL2 xx_VOL1 xx_VOL0 Volume Setting 0 dB -20 dB -40 dB - INV_A2 INV_B1 2 1 Px_ATAPI2 Px_ATAPI1 Px_ATAPI0 0 0 INV_A1 ...
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... The AOUTAx and AOUTBx volume levels are independently controlled by the A and the B Channel Volume Control registers when this function is disabled. The volume on both AOUTAx and AOUTBx are determined by the A Channel Volume Control registers (per A-B pair), and the B Channel Volume Control registers are ignored when this function is enabled. CS42428 43 ...
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... ATAPI CHANNEL MIXING AND MUTING (PX_ATAPIX) Default = 01001 Function: The CS42428 implements the channel mixing functions of the ATAPI CD-ROM specification. The ATAPI functions are applied per A-B pair. Refer to Table 15 and Figure 5 for additional information. ATAPI4 ATAPI3 ATAPI2 ...
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... LGAIN4 LGAIN3 RGAIN4 RGAIN3 Decimal Value +15 + -10 -15 Table 16. Example ADC Input Gain Settings DE-EMPH0 INT1 CS42428 2 1 LGAIN2 LGAIN1 2 1 RGAIN2 RGAIN1 Volume Setting + - INT0 Reserved Reserved 0 LGAIN0 ...
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... PLL UNLOCK (UNLOCK) Default = 0 Function: PLL unlock status bit. This bit will go high if the PLL becomes unlocked. 5.18.2 ADC OVERFLOW (OVERFLOW) Default = 0 Function: Indicates that there is an over-range condition anywhere in the CS42428 ADC signal path Reserved Reserved CS42428 ...
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... Active low 1 - Active high Function: Determines the polarity of the MUTEC pin Reserved Reserved Reserved Reserved Reserved Reserved M_AOUTA1 M_AOUTB1 CS42428 2 1 Reserved OverFlowM Reserved 2 1 Reserved OF1 Reserved Reserved OF0 Reserved 2 1 M_AOUTA2 M_AOUTA3 M_AOUTA4 M_AOUTB2 M_AOUTB3 M_AOUTB4 ...
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... It is recommended that in this mode this bit be set to 0. GPO, Drive High Mode - If the pin is configured as a general purpose output driven high, the polarity bit is ignored recommended that in this mode this bit be set Function4 Function3 CS42428 Function2 Function1 Function0 ...
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... M_AOUTA1 M_AOUTA2 M_AOUTA3 M_AOUTB1 M_AOUTB2 M_AOUTB3 M_AOUTA1 M_AOUTA2 M_AOUTA3 M_AOUTB1 M_AOUTB2 M_AOUTB3 Function0 GPOx 0 0 Drive Low 1 1 OVFL CS42428 Function1 Function0 M_AOUTA3 M_AOUTA4 M_AOUTB3 M_AOUTB4 M_AOUTA3 M_AOUTA4 M_AOUTB3 M_AOUTB4 M_AOUTA3 M_AOUTA4 M_AOUTB3 M_AOUTB4 M_AOUTB3 M_AOUTA4 M_AOUTB4 M_AOUTB3 M_AOUTA4 M_AOUTB4 ...
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... C.) A SPECIFIED OPERATING CONDITIONS to ground; OMCK=12.288 MHz; Master Mode) Parameter DC Power Supply Serial data port interface power Ambient Operating Temperature (power applied) CS42428-CQ ABSOLUTE MAXIMUM RATINGS Parameters DC Power Supply Serial data port interface power Input Current Analog Input Voltage ...
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... THD -100 - - -97 108 114 105 111 - 108 THD -100 - - -97 - 110 - 0.0001 - 0.1 - +/-100 - 0 - 100 1.9 2 CMRR - 0.01 CS42428 CS42428-DQ Max Min Typ Max - 106 114 - - 103 111 - -94 - -100 - - - 106 114 - - 103 111 - - - 108 - -94 - -100 - - - - ...
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... Notes: 6. The filter frequency response scales precisely with Fs. 7. Response shown is for Fs equal to 48 kHz. Filter characteristics scale with Symbol (Note 6) (Note ∆t gd (Note 6) (Note ∆t gd (Note 6) (Note ∆t gd (Note 7) (Note 7) CS42428 - 5 Ω 0. Min Typ Max Unit 0 - 0.47 Fs ±0.035 - - ...
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... Figure 21. Single Speed Mode Transition Band 0.10 0.08 0.05 0.03 0.00 -0.03 -0.05 -0.08 -0.10 0.52 0.53 0.54 0.55 0.00 0.05 0.10 Figure 23. Single Speed Mode Passband Ripple 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0.40 0.43 0.45 0.7 0.8 0.9 1.0 Figure 25. Double Speed Mode Transition Band CS42428 0.46 0.48 0.50 0.52 0.54 0.56 0.58 Frequency (normalized to Fs) 0.15 0.20 0.25 0.30 0.35 0.40 Frequency (normalized to Fs) 0.48 0.50 0.53 0.55 0.58 0.60 0.63 0.65 Frequency (normalized to Fs) 0.60 0.45 0.50 0.68 0.70 53 ...
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... Figure 30. Quad Speed Mode Transition Band (Detail) 54 0.10 0.08 0.05 0.03 0.00 -0.03 -0.05 -0.08 -0.10 0.50 0.53 0.55 0.00 0.05 Figure 27. Double Speed Mode Passband Ripple 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0.7 0.8 0.9 1.0 0.2 0.25 Figure 29. Quad Speed Mode Transition Band 0.10 0.08 0.06 0.04 0.02 0.00 -0.02 -0.04 -0.06 -0.08 -0.10 0.4 0.45 0.5 0.55 0.6 0.00 Figure 31. Quad Speed Mode Passband Ripple CS42428 0.10 0.15 0.20 0.25 0.30 0.35 0.40 Frequency (normalized to Fs) 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 Frequency (normalized to Fs) 0.05 0.10 0.15 0.20 Frequency (normalized to Fs) 0.45 0.50 0.75 0.8 0.25 ...
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... L L CS42428-CQ Symbol Min Typ 108 114 105 111 - THD -100 - - -94 - -74 - -34 - 114 - 90 .88VA .92VA - 0.1 - 100 Z - 100 OUT CS42428 CS42428-DQ Max Min Typ Max - 108 114 - - 105 111 - - - -94 - -100 - - - - - - 114 - - - 90 - .94VA .88VA ...
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... kHz - - Fs = 44.1 kHz - - kHz - - -0.01 - 0.5834 - (Note 11 4.6/ kHz - - -0.01 - 0.6355 - (Note 11 4.7/ kHz - - CS42428 Slow Roll-Off Max Min Typ 0.4535 0 - 0.4166 0.4998 0 - 0.4998 +0.01 -0.01 - +0.01 - 0.5834 - - 6.5/Fs ±0.41/Fs - ±0.14/Fs ±0. ±0.23 ±0. ±0.14 ±0. ±0.09 0.4166 0 - 0.2083 0.4998 ...
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... Figure 36. Single Speed (slow) Stopband Rejection 100 120 0.4 0.42 0.8 0.9 1 Figure 33. Single Speed (fast) Transition Band 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 0.52 0.53 0.54 0.55 0 0.05 Figure 35. Single Speed (fast) Passband Ripple 100 120 0.8 0.9 1 0.4 0.42 Figure 37. Single Speed (slow) Transition Band CS42428 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 Frequency(normalized to Fs) 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 Frequency(normalized to Fs) 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 Frequency(normalized to Fs) 0.6 0.5 0.6 57 ...
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... Figure 42. Double Speed (fast) Transition Band (detail) 58 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 0 0.05 0.52 0.53 0.54 0.55 Figure 39. Single Speed (slow) Passband Ripple 100 120 0.4 0.42 0.8 0.9 1 Figure 41. Double Speed (fast) Transition Band 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 0.52 0.53 0.54 0.55 0 0.05 Figure 43. Double Speed (fast) Passband Ripple CS42428 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 Frequency(normalized to Fs) 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 Frequency(normalized to Fs) 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 Frequency(normalized to Fs) 0.5 0.6 0.5 ...
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... Figure 48. Quad Speed (fast) Stopband Rejection 100 120 0.2 0.7 0.8 0.9 1 Figure 45. Double Speed (slow) Transition Band 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 0.52 0.53 0.54 0.55 0 Figure 47. Double Speed (slow) Passband Ripple 100 120 0.2 0.7 0.8 0.9 1 Figure 49. Quad Speed (fast) Transition Band CS42428 0.3 0.4 0.5 0.6 0.7 Frequency(normalized to Fs) 0.05 0.1 0.15 0.2 0.25 0.3 Frequency(normalized to Fs) 0.3 0.4 0.5 0.6 0.7 Frequency(normalized to Fs) 0.8 0.35 0.8 59 ...
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... Figure 54. Quad Speed (slow) Transition Band (detail) 60 0.2 0.15 0.1 0.05 0 0.05 0.1 0.15 0.2 0 0.52 0.53 0.54 0.55 Figure 51. Quad Speed (fast) Passband Ripple 100 120 0.1 0.7 0.8 0.9 1 Figure 53. Quad Speed (slow) Transition Band 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 0.51 0.52 0.53 0.54 0.55 0 Figure 55. Quad Speed (slow) Passband Ripple CS42428 0.05 0.1 0.15 0.2 Frequency(normalized to Fs) 0.2 0.3 0.4 0.5 0.6 0.7 0.8 Frequency(normalized to Fs) 0.02 0.04 0.06 0.08 0.1 Frequency(normalized to Fs) 0.25 0.9 0.12 ...
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... DAC_LRCK, ADC_LRCK Edge to DAC_SCLK, ADC_SCLK Rising Notes: 13. After powering up the CS42428, RST should be held low after the power supplies and clocks are settled. 14. See Table 2 on page 15 for suggested OMCK frequencies 15. Limit the loading on RMCK to 1 CMOS load if operating above 24.576 MHz. ...
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... Double-Speed Mode, -------------------- - × 128 Fs t high t t sud t ack hdd Figure 58. Control Port Timing - I CS42428 2 C FORMAT (For CQ, T Min Max - 100 500 - 4.7 - 4.0 - 4.7 - 4 250 - - 1 - 300 4 (Note 18 SCL ...
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... =VLS= 3.3 V; VLC = 1 5. pF) L Symbol (Note 19 (Note 20) (Note 21) (Note 21) t scl t sch t css dsu Figure 59. Control Port Timing - SPI Format CS42428 Min Typ Max 0 - 6.0 sck 1 csh css scl 66 - ...
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... PSRR (60 Hz) (For CQ, T Symbol Serial Port V Control Port IH Serial Port V Control Port IL (Note 27)Serial Port V Control Port OH MUTEC, GPOx (Note 27 CS42428 Min Typ Max Units - 150 - - 100 - - 250 - - 250 - - 250 - - 780 850 - 1 ...
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... Gain Error The deviation from the nominal full-scale analog output for a full-scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/°C. Offset Error The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV. CS42428 65 ...
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... Cirrus Logic, A Fifth-Order Delta-Sigma Modulator with 110 dB Audio Dynamic Range Fuji- mori, K. Hamashita and E.J. Swanson. Paper presented at the 93rd Convention of the Audio Engineer- ing Society, October 1992. 9) Philips Semiconductor, The I tors.philips.com 66 2 C-Bus Specification: Version 2.1, Jan. 2000. http://www.semiconduc- CS42428 ...
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... L INCHES NOM MAX 0.55 0.063 0.004 0.006 0.008 0.011 0.472 BSC 0.484 0.393 BSC 0.398 0.472 BSC 0.484 0.393 BSC 0.398 0.020 BSC 0.024 0.024 0.030 4° 7.000° CS42428 A A1 MILLIMETERS MIN NOM --- 1.40 0.05 0.10 0.17 0.20 11.70 12.0 BSC 9.90 10.0 BSC 11.70 12.0 BSC 9.90 10.0 BSC 0.40 0.50 BSC 0.45 0.60 0.00° 4° ...