ICM7211ALM44 INTERSIL [Intersil Corporation], ICM7211ALM44 Datasheet - Page 10

• Manufacturer Part Number: ICM7211ALM44
• Description: 4-Digit, ICM7211 (LCD) and ICM7212 (LED) Display Drivers
• Manufacturer: INTERSIL [Intersil Corporation]

elevated temperatures the segment current be limited by use
of the brightness input to keep power dissipation within the
limits described above.
Input Configurations and Output Codes
The standard devices in the ICM7211 and ICM7212 family
accept a four-bit true binary (i.e., positive level = logical one)
input at pins 27 thru 30, least significant bit at pin 27 ascend-
ing to the most significant bit at pin 30. The ICM7211 and
ICM7211M devices decode this binary input into a seven-
segment alphanumeric hexadecimal output, while the
ICM7211A, ICM7211AM, and ICM7212AM decode the
binary input into seven-segment alphanumeric “Code B” out-
put, i.e., 0-9, dash, E, H, L, P, blank. These codes are shown
explicitly in Table 1. Either decoder option will correctly
decode true BCD to a seven-segment decimal output.
B3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
B2
BlNARY
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
B1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
TABLE 1. OUTPUT CODES
BO
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
HEXADECIMAL
ICM7211M
ICM7211
ICM7212AM
ICM7211A
CODE B
BLANK
ICM7211, ICM7212
9-15
These devices are actually mask-programmable to provide
any 16 combinations of the seven segment outputs decoded
from the four input bits. For large quantity orders custom
decoder options can be arranged. Contact the factory for
details.
The ICM7211 and ICM7211A devices are designed to accept
multiplexed binary or BCD input. These devices provide four
separate digit lines (least significant digit at pin 31 ascending
to most significant digit at pin 34), each of which when taken
to a positive level decodes and stores in the output latches of
its respective digit the character corresponding to the data at
the input port, pins 27 through 30.
The ICM7211M, ICM7211AM, and ICM7212AM devices are
intended to accept data from a data bus under processor
control.
In these devices, the four data input bits and the two-bit digit
address (DA1 pin 31, DA2 pin 32) are written into input buffer
latches when both chip select inputs (CS1 pin 33, CS2 pin
34) are taken low. On the rising edge of either chip select
input, the content of the data input latches is decoded and
stored in the output latches of the digit selected by the con-
tents of the digit address latches.
An address of 00 writes into D4, DA2 = 0, DA1 = 1 writes into
D3, DA2 = 1, DA1 = 0 writes into D2, and 11 writes into D1.
The timing relationships for inputting data are shown in
Figure 2, and the chip select pulse widths and data setup and
hold times are specified under Operating Characteristics.
FIGURE 10. SEGMENT ASSIGNMENT
e
f
d
g
a
c
b