LTC1294 LINER [Linear Technology], LTC1294 Datasheet

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... STRAIN GAUGE BRIDGE THREE ADDITIONAL STRAIN GAUGE INPUTS CAN BE ACCOMMODATED USING THE OTHER AMPLIFIERS IN THE LT1014 LTC1293/LTC1294/LTC1296 D ESCRIPTIO The LTC1293/4 family of data acquisition systems which contain a serial I/O successive approximation A/D converter. It uses LTCMOS ogy to perform either 12-bit unipolar, or 11-bit plus sign bipolar A/D conversions ...

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... LTC1293BCN LTC1293BIJ 10 AGND LTC1293CCN LTC1293CIJ – LTC1293DCN LTC1293DIJ LTC1294BIN LTC1294BMJ LTC1294CIN LTC1294CMJ 18 CLK LTC1294DIN LTC1294DMJ LTC1294BCN OUT LTC1294BIJ LTC1294CCN LTC1294CIJ + 14 REF LTC1294DCN LTC1294DIJ – 13 REF 12 AGND – LTC1296BIN LTC1296BMJ SSO 19 CLK 18 LTC1296CIN LTC1296CMJ 17 ...

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... CS High Time During Conversion wHCS t CS Low Time During Data Transfer wLCS t Delay Time, CLK to SSO enSSO t Delay Time SSO disSSO C Input Capacitance IN LTC1293/LTC1294/LTC1296 LTC1293/4/6B MIN TYP MAX 3.0 0.5 0.5 12 (Note 3) CONDITIONS (Note 6) CC See Operating Sequence See Operating Sequence ...

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... OUT OUT CC CS High CS High, LTC1294BC, LTC1294CC, Power LTC1294DC, LTC1294BI, Shutdown LTC1294CI, LTC1294DI, CLK Off LTC1294BM, LTC1294CM, LTC1294DM CS High CS High SSO SSO CC Note 6: Recommended operating conditions. Note 7: Two on-chip diodes are tied to each reference and analog input – ...

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... –50 –30 – 110 AMBIENT TEMPERATURE (°C) Change in Gain vs Reference Voltage –0.2 –0.4 LTC1294/6 –0.6 –0.8 –1.0 LTC1293 –1 REFERENCE VOLTAGE (V) LTC1293 G05 Change in Gain vs Temperature 0 REF CLK = 1MHz 0.4 0.3 ...

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... LTC1293/LTC1294/LTC1296 W U TYPICAL PERFOR A D Delay Time vs Temperature OUT 250 200 150 MSB FIRST DATA 100 LSB FIRST DATA 50 0 –50 – 100 125 AMBIENT TEMPERATURE (°C) LTC1293 G10 Sample and Hold Acquisition Time vs Source Resistance 100 ...

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... System Shutdown Output pin will go low when power shutdown is requested. Output 20 V Positive Supply This supply must be kept free of noise and ripple by bypassing directly to the analog ground plane. CC LTC1293/LTC1294/LTC1296 – to most negative potential in the circuit (Ground in single supply applications). – to most negative potential in the circuit (Ground in single supply applications). + – ...

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... LTC1293/LTC1294/LTC1296 AGRA BLOCK (Pin numbers refer to LTC1294 INPUT 15 D SHIFT IN REGISTER 1 CH0 2 CH1 3 CH2 4 ANALOG CH3 INPUT MUX 5 CH4 6 CH5 7 CH6 8 CH7 9 COM 10 11 – DGND V TEST CIRCUITS Load Circuit for dDO 1. OUT 100pF Load Circuit for t ...

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... SSO dis 2.4V SSO Voltage Waveform for for t CLK 0.8V t SSO en SSO 0.8V Voltage Waveform for D Delay Time, t OUT CLK 0.8V t dDO D OUT LTC1293/LTC1294/LTC1296 Voltage Waveforms for Voltage Waveform for D disSSO D OUT t r LTC1293 TC10 enSSO CS D OUT WAVEFORM 1 (SEE NOTE 1) D OUT ...

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... LTC1293/LTC1294/LTC1296 PPLICATI S I FOR ATIO A The LTC 1293/4 data acquisition component which contains the following functional blocks: 1. 12-bit successive approximation capacitive A/D converter 2. Analog multiplexer (MUX) 3. Sample and hold (S/H) 4. Synchronous, half duplex serial interface 5. Control and timing logic DIGITAL CONSIDERATIONS ...

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... PPLICATI S I FOR ATIO Table 1a. LTC1294/6 Multiplexer Channel Selection MUX ADDRESS DIFFERENTIAL CHANNEL SELECTION SGL/ ODD SELECT DIFF SIGN – – – – ...

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... LTC1293/LTC1294/LTC1296 PPLICATI S I FOR ATIO A OUTPUT CODE • • • The following discussion will demonstrate how the two reference pins are to be used in conjunction with the analog input multiplexer ...

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... SGL/ ODD/ SEL0 MSBF DIFF SIGN HI-Z D OUT t SMPL LTC1293/LTC1294/LTC1296 W U MSB-First/LSB-First (MSBF) + 4V. Note The output data of the LTC1293/4/6 is programmed for + 1V MSB-first or LSB-first sequence using the MSB bit. When the MSBF bit is a logical one, data will appear on the D line in MSB-first format. Logical zeroes will be filled in + – ...

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... LTC1293/LTC1294/LTC1296 PPLICATI S I FOR ATIO Example: Differential Inputs (CH4 CS CLK START SEL1 UNI ODD/ MSBF SEL1/ SEL0 DIFF SIGN HI-Z D OUT *STOPPING THE CLOCK WILL HELP REDUCE POWER CONSUMPTION. CS CAN BE BROUGHT HIGH ONCE THE DIN WORD HAS BEEN CLOCKED IN. ...

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... B10 B9 B8 BYTE 1 ANALOG LSB INPUTS BYTE and CLK are generated IN signal is read on a fourth OUT lines together. The 8051 first sends the OUT to the LTC1294 over the line connected to IN DON'T CARE ...

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... SGL/ ODD/ SEL DATA DIFF SIGN START IN OUT 8051 P1.2 OUTPUT DATA TO LTC1294 AS INPUT AFTER THE 8TH RISING CLK BEFORE THE 8TH FALLING CLK D OUT FROM LTC1294 STORED IN 8051 RAM MSB B11 B10 B9 LSB LABEL MNEMONIC OPERAND COMMENTS ...

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... SETB P1.3 CLK GOES HIGH OUTPUT PORT Figure 3. Several LTC1294 Sharing One 3-Wire Serial Interface Sharing the Serial Interface The LTC1293/4/6 can share the same 3-wire serial inter- face with other peripheral components or other LTC1293/ 4/6’s (Figure 3). Now, the CS signals decide which LTC1293/ 4/6 is being addressed by the MPU ...

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... PPLICATI S I FOR ATIO LTC1294. Figure 4 shows an example of an ideal LTC1293/ 4/6 ground plane design for a two sided board. Of course this much ground plane will not always be possible, but users should strive to get as close to this ideal as possible TANTALUM ...

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... CS CLK D IN START D OUT (+) INPUT (–) INPUT LTC1293/LTC1294/LTC1296 W U “–” Input Settling At the end of the sample phase the input capacitor switches ). C to the “-” input and the conversion starts (see Figure 8 During the conversion, the “+” input voltage is effectively “ ...

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... LTC1293/LTC1294/LTC1296 PPLICATI S I FOR ATIO A within the minimum settling windows of 2.5 s (“+” input) and 1 s(“–” input) that occurs at the maximum clock rate of 1MHz. Figures 9 and 10 show examples of adequate and poor op amp settling. HORIZONTAL: 500ns/DIV Figure 9. Adequate Settling of Op Amp Driving Analog Input HORIZONTAL: 20 s/DIV Figure 10 ...

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... For example the LT1027 will settle adequately or with bypass capacitor at V LT1021 also can be used. LTC1293/LTC1294/LTC1296 W U Figure 13. Adequate Reference Settling (LT1027) Figure 14. Poor Reference Settling Can Cause A/D Errors ...

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... Gain Error due to Reduced V REF The gain error of the LTC1294/6 is very good over a wide range of reference voltages. The error component that is seen in the typical performance characteristics curve Change in Gain Error vs Reference Voltage for the LTC1293 is due the voltage drop on the AGND pin from the device to the ground plane ...

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... SUPPLY 9.0 8 45.4kHz S 8 FREQUENCY (kHz) Figure 17. LTC1294 ENOB vs Input Frequency LTC1293/LTC1294/LTC1296 W U –20 –40 –60 –80 –100 –120 –140 20 25 1293 F16a For +5V supplies the ENOB decreases more rapidly. This is due predominantly to the 2nd harmonic distortion term. Figure 18 shows a FFT plot of the output spectrum for two tones applied to the input of the A/D ...

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... LTC1293/LTC1294/LTC1296 PPLICATI S I FOR ATIO This means four channels can handle 7mA of input current each. Reducing CLK frequency from a maximum of 1MHz (See typical performance characteristics curves Maxi- mum CLK Frequency vs Source Resistance and Sample and Hold Acquisition Time vs Source Resistance) allows the use of larger current limiting resistors. The “ ...

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... PPLICATI S I FOR ATIO A “Quick Look” Circuit for the LTC1294/6 Users can get a quick look at the function and timing of the LTC1294/6 by using the following simple circuit (Figure 23 tied tied high which means V REF CC IN should be applied to the CH7 with respect to COM. A 22µ ...

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... CH6 REF – CH7 REF COM AGND – DGND V *SOLID TANTALUM 26 S 4N28s 10k 9V 10k 2N3906 51k 51k 5.1k (3) 51k 51k TO ADDITIONAL LTC1294s 300 4N28 10k 2N3904 4N28 ISOLATION BARRIER NC 5V 10k 2N3906 C1 150 5V 10k SCK 150 5V 10k C0 150 TO 68HC11 5V 10k MOSI 150 5 ...

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... Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of circuits as described herein will not infringe on existing patent rights. LTC1293/LTC1294/LTC1296 U Dimensions in inches (millimeters) unless otherwise noted. ...

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... LTC1293/LTC1294/LTC1296 PACKAGE DESCRIPTIO 0.300 – 0.325 0.130 ± 0.005 (7.620 – 8.255) (3.302 ± 0.127) 0.015 (0.381) MIN 0.009 – 0.015 (0.229 – 0.381) +0.025 0.325 –0.015 0.125 0.065 ± 0.015 ( +0.635 ) (3.175) (1.651 ± 0.381) 8.255 –0.381 MIN 0.100 ± ...