HLMP-ED80-XX000 AVAGO [AVAGO TECHNOLOGIES LIMITED], HLMP-ED80-XX000 Datasheet - Page 21
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HLMP-ED80-XX000
Manufacturer Part Number
HLMP-ED80-XX000
Description
Optical Mouse Sensor
Manufacturer
AVAGO [AVAGO TECHNOLOGIES LIMITED]
Datasheet
1.HLMP-ED80-XX000.pdf
(40 pages)
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21
The falling edge of SCLK for the first address bit of either the read or write command must be at least 120 ns after the
last SCLK rising edge of the last data bit of the previous read operation.
Figure 33. Timing between read and either write or subsequent read commands
Figure 34. Timing between SCLK and PD rising edge
SCLK
SCLK
PD
ADNS-2051 fig 34
ADDRESS
DATA
>1 µs
READ OPERATION
t
HOLD
ADNS-2051 fig 33
>100 µs
DATA
t
SRW
, t
OR WRITE OPERATION
SRR
>120 µs
NEXT READ
ADDRESS
• • •
• • •
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